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    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY
    11.
    发明申请
    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY 有权
    电阻记忆体中的参考电平的系统和方法

    公开(公告)号：US20160125926A1

    公开(公告)日：2016-05-05

    申请号：US14992753

    申请日：2016-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

    Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

    Abstract translation: 一种方法包括在电阻式存储器件中，基于第一有效参考电阻和第二有效参考电阻来确定平均有效参考电阻电平。 第一有效参考电阻基于电阻性存储器件的第一组参考单元，第二有效参考电阻基于电阻式存储器件的第二组参考单元。 该方法包括至少部分地基于平均有效参考电阻电平来修整参考电阻。 响应于确定第一有效参考电阻基本上不等于平均有效参考电阻电平，修整参考电阻包括修改与第一有效参考电阻相关联的一个或多个磁性隧道结装置的一个或多个状态。

    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION
    12.
    发明申请
    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION 有权
    感应放大器偏置电压降低

    公开(公告)号：US20150022264A1

    公开(公告)日：2015-01-22

    申请号：US13947144

    申请日：2013-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

    IPC: G01R31/28 ,  H03F1/00

    CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

    Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

    Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

    Dynamic memory protection
    13.
    发明授权
    Dynamic memory protection 有权

    公开(公告)号：US10740017B2

    公开(公告)日：2020-08-11

    申请号：US15963668

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

    IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

    Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory
    15.
    发明授权
    Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory 有权

    公开(公告)号：US10460780B2

    公开(公告)日：2019-10-29

    申请号：US15939923

    申请日：2018-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

    IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

    Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

    Dynamic memory protection
    16.
    发明授权
    Dynamic memory protection 有权

    公开(公告)号：US10249814B1

    公开(公告)日：2019-04-02

    申请号：US15947660

    申请日：2018-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Chando Park ,  Seung Kang ,  Sungryul Kim ,  Wei-Chuan Chen

    IPC: G11C11/00 ,  H01L43/02 ,  G01R33/09 ,  G11C11/16 ,  H01L43/08

    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

    Data bit inversion tracking in cache memory to reduce data bits written for write operations
    17.
    发明授权
    Data bit inversion tracking in cache memory to reduce data bits written for write operations 有权

    公开(公告)号：US10115444B1

    公开(公告)日：2018-10-30

    申请号：US15672992

    申请日：2017-08-09

    Applicant: QUALCOMM Incorporated

    Inventor： Hyunsuk Shin ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16 ,  G06F13/42 ,  G06F11/10 ,  H03M13/29 ,  G11C29/50 ,  G11C29/04 ,  G11C13/00

    Abstract: Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERROR RATE (WER) TO IMPROVE WER YIELD, AND RELATED METHODS AND SYSTEMS
    18.
    发明申请
    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERROR RATE (WER) TO IMPROVE WER YIELD, AND RELATED METHODS AND SYSTEMS 有权
    基于写错误率（WER）来调整电阻记忆写驱动强度，以提高功能，以及相关方法和系统

    公开(公告)号：US20160276009A1

    公开(公告)日：2016-09-22

    申请号：US14818809

    申请日：2015-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

    IPC: G11C11/16 ,  G11C29/44

    CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

    Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

    Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

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