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    Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods
    11.
    发明授权
    Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods 有权

    公开(公告)号：US12160952B2

    公开(公告)日：2024-12-03

    申请号：US17934651

    申请日：2022-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

    IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46

    Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

    Toroid inductor with reduced electromagnetic field leakage
    13.
    发明授权
    Toroid inductor with reduced electromagnetic field leakage 有权

    公开(公告)号：US10170232B2

    公开(公告)日：2019-01-01

    申请号：US14931659

    申请日：2015-11-03

    Applicant: QUALCOMM Incorporated

    Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane

    IPC: H01F27/28 ,  H01F27/29 ,  H01L27/08 ,  H01F41/04 ,  H05K1/18 ,  H01F17/00 ,  H01F17/02

    Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

    STAGGERED POWER STRUCTURE IN A POWER DISTRIBUTION NETWORK (PDN)
    15.
    发明申请
    STAGGERED POWER STRUCTURE IN A POWER DISTRIBUTION NETWORK (PDN) 审中-公开
    电力分配网络中的分层电力结构（PDN）

    公开(公告)号：US20150313006A1

    公开(公告)日：2015-10-29

    申请号：US14264836

    申请日：2014-04-29

    Applicant: QUALCOMM Incorporated

    Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

    IPC: H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H05K1/0216 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5286 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0236 ,  H05K2201/09309

    Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

    Abstract translation: 一些新颖的特征涉及包括第一金属层和第二金属层的集成器件。 第一金属层包括第一组区域。 第一组区域包括用于集成设备的配电网络（PDN）的第一网表结构。 第二金属层包括第二组区域。 第二组区域包括集成设备的PDN的第二网表结构。 在一些实现中，第二金属层还包括第三组区域，其包括用于集成设备的PDN的第一网表结构。 在一些实现中，第一金属层包括第三组区域，其包括用于集成设备的PDN的第三网表结构。 第三组区域与第一金属层的第一组区域不重叠。

    Package comprising channel interconnects located between solder interconnects
    16.
    发明授权
    Package comprising channel interconnects located between solder interconnects 有权

    公开(公告)号：US12243855B2

    公开(公告)日：2025-03-04

    申请号：US17532754

    申请日：2021-11-22

    Applicant: QUALCOMM Incorporated

    Inventor： Aniket Patil ,  Durodami Lisk ,  Hong Bok We ,  Charles David Paynter

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

    Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

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