公开(公告)号：US09349473B1

公开(公告)日：2016-05-24

申请号：US14619074

申请日：2015-02-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Wen Chen ,  Wei-Yung Chen

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C27/02 ,  G11C27/024

Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating a sensing voltage pair according to the differential signal, where the sensing voltage pair includes a first sensing voltage and a second sensing voltage, a voltage value of the first sensing voltage is related to a first differential signal of the differential signal, and a voltage value of the second sensing voltage is related to a second differential signal of the differential signal; and receiving the sensing voltage pair and outputting a sampling data stream according to a clock of the differential signal and a voltage relative relationship of the sensing voltage pair.

Abstract translation: 提供数据采样电路模块，数据采样方法和存储器存储装置。 该方法包括：接收差分信号并根据差分信号产生感测电压对，其中感测电压对包括第一感测电压和第二感测电压，第一感测电压的电压值与第一差分 差分信号的信号和第二感测电压的电压值与差分信号的第二差分信号相关; 并接收感测电压对，并根据差分信号的时钟和感测电压对的电压相对关系输出采样数据流。

公开(公告)号：US20160134292A1

公开(公告)日：2016-05-12

申请号：US14578471

申请日：2014-12-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Wei-Yung Chen

IPC: H03L7/08 ,  G11C7/22 ,  H03K5/159

CPC classification number: G11C7/222 ,  G11C7/1066 ,  H03K5/159 ,  H03L7/0812

Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method are provided. The sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.

Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括延迟锁定环（DLL）和采样电路。 DLL包括时钟控制电路，时钟延迟电路和电压控制电路。 时钟控制电路对参考时钟信号执行延迟锁定，以输出选择信号。 时钟延迟电路根据选择信号延迟参考时钟信号，以输出延迟时钟信号。 电压控制电路根据选择信号调整输出到时钟控制电路和时钟延迟电路的驱动电压。 采样电路根据延迟时钟信号对数据信号进行采样。 因此，可以通过调整驱动电压来提高DLL的延迟能力。

公开(公告)号：US20150052378A1

公开(公告)日：2015-02-19

申请号：US14061719

申请日：2013-10-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Yung Chen

IPC: G06F1/06 ,  G06F12/02 ,  G05D23/19

CPC classification number: G06F12/0246 ,  G06F1/06 ,  G06F13/4072 ,  G06F2213/3804 ,  H03L1/022 ,  H03L1/026 ,  H03L7/087 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/0331

Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand.

Abstract translation: 提供了连接接口单元和没有晶体振荡器的存储器，并且包括频率检测器，相位检测器，振荡器，采样电路和发射器电路。 频率检测器和相位检测器分别检测来自主机系统的输入信号与参考信号之间的频差和相位差，以产生频率信号和相位信号。 已经通过滤波器的频率信号和相位信号被发送到振荡器以产生用于产生时钟信号的参考信号。 采样电路根据参考信号产生输入数据信号。 发射机电路根据时钟信号对输出数据信号进行调制，以产生并向主机系统发送输出信号。 因此，连接接口单元符合变速器架的规格。

公开(公告)号：US20150003139A1

公开(公告)日：2015-01-01

申请号：US14011773

申请日：2013-08-28

Applicant: Phison Electronics Corp.

Inventor： Wei-Yung Chen ,  Yan-An Lin

IPC: G11C5/02 ,  H03L7/00

CPC classification number: G11C5/025 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/08 ,  H03L7/18

Abstract: A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced.

Abstract translation: 提供了设置在多个层上的存储器存储装置，存储器控制电路单元和时钟调整电路。 时钟调整电路包括检测电路，控制电压产生电路和压控振荡器（VCO）。 检测电路检测输入信号和输出信号之间的信号特性差，以产生第一信号。 控制电压产生电路耦合到检测电路，并根据第一信号产生控制电压。 VCO耦合到控制电压产生电路并且包括电感器和电容器。 VCO接收控制电压，并根据电感器和电容器的阻抗特性开始振荡，以产生输出信号。 电感器设置在层之间的衬垫层上。 由此，制造成本降低。

公开(公告)号：US20140101367A1

公开(公告)日：2014-04-10

申请号：US13692981

申请日：2012-12-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  Wei-Yung Chen ,  Ming-Hui Tseng

IPC: G06F12/02 ,  H04B1/16

CPC classification number: G06F12/0238 ,  G06F1/3215 ,  G06F1/3278 ,  H04B1/1615 ,  H04W52/0229 ,  Y02D10/157 ,  Y02D70/00

Abstract: A controlling method for connector is provided, which includes: receiving a first signal stream under a condition that a squelch detector is turned-off; determining whether the first signal stream contains a burst signal under a first operating frequency; if the first signal stream contains the burst signal, turning on the squelch detector and determining by the squelch detector under a second operating frequency whether a second signal stream is a waking signal, wherein the second signal stream is received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency. The controlling method further includes: if the second signal stream is the waking signal, changing an operating state of the connector to an active state. In this way, the power consumption of the connector is reduced.

Abstract translation: 提供了一种用于连接器的控制方法，包括：在静噪检测器关闭的条件下接收第一信号流; 确定所述第一信号流是否包含在第一工作频率下的突发信号; 如果第一信号流包含突发信号，则打开静噪检测器并且在第二工作频率下由静噪检测器确定第二信号流是否是唤醒信号，其中在接收到第一信号流之后接收第二信号流，以及 第二工作频率大于第一工作频率。 控制方法还包括：如果第二信号流是唤醒信号，则将连接器的操作状态改变为活动状态。 以这种方式，连接器的功耗降低。

公开(公告)号：US10326622B2

公开(公告)日：2019-06-18

申请号：US15836903

申请日：2017-12-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Wen Chen ,  Shin-Yang Sun ,  Wei-Yung Chen ,  Jen-Chu Wu ,  Chih-Ming Chen

IPC: H04L25/03 ,  H04L25/497 ,  H04L7/00 ,  G06F3/06

Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.

公开(公告)号：US20180205224A1

公开(公告)日：2018-07-19

申请号：US15452742

申请日：2017-03-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Shin Chang ,  Wei-Yung Chen

IPC: H02H9/04 ,  G11C16/08 ,  G11C16/22 ,  G11C29/04 ,  H03K17/16 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C7/10 ,  G11C2029/0411 ,  G11C2207/105 ,  H01L27/0288 ,  H02H9/046

Abstract: An exemplary embodiment of the disclosure provides a switch module which includes a first conductive unit, a first switch unit and a first electrostatic protection module. The first electrostatic protection module is coupled between the first conductive unit and the first switch unit. The first electrostatic protection module includes a first protection circuit and a first inductor circuit. The first inductor circuit includes a first inductor unit, and the first inductor circuit is coupled between the first protection circuit and the first conductive unit. Accordingly, the transmission efficiency of the switch (or multiplexer) for high speed signal can be improved.

公开(公告)号：US20180165241A1

公开(公告)日：2018-06-14

申请号：US15429175

申请日：2017-02-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Ting Wei ,  Wei-Yung Chen ,  Yun-Chieh Chen ,  Ta-Chuan Wei

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282

Abstract: A channel switching device, a memory storage device and a channel switching method are provided. The channel switching device includes a signal analysis module and a switch module. The signal analysis module is configured to analyze non-power signal from at least one of a plurality of connection interface units of the memory storage device. The switch module is configured to turn on a first channel coupled to a first connection interface unit among the connection interface units of the memory storage device according to an analysis result of the non-power signal, where the first channel which is turned on is for receiving first input signal from the first connection interface unit or transmitting first output signal to the first connection interface unit. Therefore, a probability of mistakenly enabling or disabling a specific connection interface unit of a memory storage device can be reduced.

公开(公告)号：US09467314B1

公开(公告)日：2016-10-11

申请号：US14855389

申请日：2015-09-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Ting Wei ,  Sheng-Wen Chen ,  Wei-Yung Chen ,  Chih-Ming Chen

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0058

Abstract: A signal modulation method, an adaptive equalizer and a memory storage device are provided. The method includes: receiving a first signal; performing a first modulation on the first signal based on a first power mode to generate a second signal having a first eye-width; performing a second modulation based on a second power mode to generate the second signal having a second eye-width; determining whether the first eye-width and the second eye-width meet a first condition; if yes, performing a third modulation based on the first power mode to generate the second signal having a third eye-width; otherwise, performing the third modulation based on the second power mode to generate the second signal having the third eye-width. Therein, a power consumption of performing the second modulation is less than that of performing the first modulation. Therefore, an efficiency of the adaptive equalizer may be improved.

Abstract translation: 提供信号调制方法，自适应均衡器和存储器存储装置。 该方法包括：接收第一信号; 基于第一功率模式对所述第一信号执行第一调制以产生具有第一眼睛宽度的第二信号; 基于第二功率模式执行第二调制以产生具有第二眼睛宽度的第二信号; 确定第一眼睛宽度和第二眼睛宽度是否满足第一条件; 如果是，则基于第一功率模式执行第三调制以产生具有第三眼睛宽度的第二信号; 否则，基于第二功率模式执行第三调制以产生具有第三眼睛宽度的第二信号。 其中，执行第二调制的功耗小于执行第一调制的功耗。 因此，可以提高自适应均衡器的效率。

公开(公告)号：US09311231B2

公开(公告)日：2016-04-12

申请号：US14061719

申请日：2013-10-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Yung Chen

IPC: G06F12/02 ,  H04L7/033 ,  G06F13/40 ,  G06F1/06

CPC classification number: G06F12/0246 ,  G06F1/06 ,  G06F13/4072 ,  G06F2213/3804 ,  H03L1/022 ,  H03L1/026 ,  H03L7/087 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/0331

Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand.

Abstract translation: 提供了连接接口单元和没有晶体振荡器的存储器，并且包括频率检测器，相位检测器，振荡器，采样电路和发射器电路。 频率检测器和相位检测器分别检测来自主机系统的输入信号与参考信号之间的频差和相位差，以产生频率信号和相位信号。 已经通过滤波器的频率信号和相位信号被发送到振荡器以产生用于产生时钟信号的参考信号。 采样电路根据参考信号产生输入数据信号。 发射机电路根据时钟信号对输出数据信号进行调制，以产生并向主机系统发送输出信号。 因此，连接接口单元符合变速器架的规格。