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公开(公告)号：US20230048903A1
公开(公告)日：2023-02-16
申请号：US17468711
申请日：2021-09-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Guan-Wei Wu , Jen-Chu Wu , Jen-Huo Wang , Yu-Chiang Liao , Shih-Yang Sun
Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
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公开(公告)号：US11101003B1
公开(公告)日：2021-08-24
申请号：US16805848
申请日：2020-03-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Bo-Jing Lin , Yu-Chiang Liao
Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.
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公开(公告)号：US11075637B2
公开(公告)日：2021-07-27
申请号：US16702495
申请日：2019-12-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.
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公开(公告)号：US20210143822A1
公开(公告)日：2021-05-13
申请号：US16702495
申请日：2019-12-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.
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公开(公告)号：US10749728B1
公开(公告)日：2020-08-18
申请号：US16362725
申请日：2019-03-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.
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Patent Agency Ranking
公开(公告)号：US20190116069A1
公开(公告)日：2019-04-18
申请号：US15836903
申请日：2017-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sheng-Wen Chen , Shin-Yang Sun , Wei-Yung Chen , Jen-Chu Wu , Chih-Ming Chen
IPC: H04L25/03 , G06F3/06 , H04L7/00 , H04L25/497
Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.
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7.发明申请SAMPLING CIRCUIT MODULE, MEMORY CONTROL CIRCUIT UNIT, AND DATA SAMPLING METHOD 审中-公开采样电路模块，存储器控制电路单元和数据采集方法公开(公告)号：US20160134292A1
公开(公告)日：2016-05-12
申请号：US14578471
申请日：2014-12-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen
CPC classification number: G11C7/222 , G11C7/1066 , H03K5/159 , H03L7/0812
Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method are provided. The sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括延迟锁定环（DLL）和采样电路。 DLL包括时钟控制电路，时钟延迟电路和电压控制电路。 时钟控制电路对参考时钟信号执行延迟锁定，以输出选择信号。 时钟延迟电路根据选择信号延迟参考时钟信号，以输出延迟时钟信号。 电压控制电路根据选择信号调整输出到时钟控制电路和时钟延迟电路的驱动电压。 采样电路根据延迟时钟信号对数据信号进行采样。 因此，可以通过调整驱动电压来提高DLL的延迟能力。
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8.发明授权Signal transmission circuit and method for detecting signal transmission interface 有权信号传输电路及信号传输接口检测方法公开(公告)号：US08837630B2
公开(公告)日：2014-09-16
申请号：US13853056
申请日：2013-03-29
Applicant: Phison Electronics Corp.
Inventor： Jen-Chu Wu
CPC classification number: H04L25/0266
Abstract: A signal transmission circuit of an electronic device is provided. The electronic device is coupled to a signal reception circuit of a host via the signal transmission circuit. The signal transmission circuit includes a driving circuit module and a signal detection module. The driving circuit module provides at least one initialized signal and a detection signal. The initialized signal is output prior to the detection signal. The signal detection module is coupled to the signal reception circuit via a signal detection terminal. The initialized signal reduces a signal reference level of a reception terminal of the signal reception circuit. The signal detection module determines the type of the transmission interface of the signal reception circuit according to whether the detection signal of the signal detection terminal satisfies a predetermined threshold value. Furthermore, a method for detecting the signal transmission interface is provided.
Abstract translation: 提供电子设备的信号传输电路。 电子设备经由信号传输电路耦合到主机的信号接收电路。 信号传输电路包括驱动电路模块和信号检测模块。 驱动电路模块提供至少一个初始化信号和检测信号。 初始化信号在检测信号之前被输出。 信号检测模块通过信号检测端子耦合到信号接收电路。 初始化信号降低信号接收电路的接收端的信号参考电平。 信号检测模块根据信号检测端子的检测信号是否满足预定的阈值来确定信号接收电路的传输接口的类型。 此外，提供了一种用于检测信号传输接口的方法。
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公开(公告)号：US20230164008A1
公开(公告)日：2023-05-25
申请号：US17543741
申请日：2021-12-07
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chun-Wei Chang , Ching-Jui Hsiao , Jen-Chu Wu , Yuwei Kuo
IPC: H04L25/49
CPC classification number: H04L25/4904
Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device. The path control circuit may control the multipath signal transmission circuit to switch to perform second signal transmission between the upstream device and the downstream device based on the first signal transmission frequency and the first signal transmission path according to the first data sequence.
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公开(公告)号：US11575496B1
公开(公告)日：2023-02-07
申请号：US17547241
申请日：2021-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Ching-Jui Hsiao , Chun-Wei Chang , Sheng-Wen Chen , Ching-Chung Cheng
Abstract: A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.
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