公开(公告)号：US20210191453A1

公开(公告)日：2021-06-24

申请号：US16736819

申请日：2020-01-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Wen Chen ,  Shih-Yang Sun ,  Zhen-Hong Hung

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076 ,  G11C11/4074 ,  H03L7/08

Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.

公开(公告)号：US20230048903A1

公开(公告)日：2023-02-16

申请号：US17468711

申请日：2021-09-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Guan-Wei Wu ,  Jen-Chu Wu ,  Jen-Huo Wang ,  Yu-Chiang Liao ,  Shih-Yang Sun

IPC: G11C16/32 ,  G11C7/22 ,  G11C7/10 ,  G11C29/12

Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

公开(公告)号：US11062781B1

公开(公告)日：2021-07-13

申请号：US16916137

申请日：2020-06-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Zhen-Hong Hung ,  Shih-Yang Sun ,  Sheng-Wen Chen

IPC: G11C16/32

Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.

公开(公告)号：US20240310870A1

公开(公告)日：2024-09-19

申请号：US18306974

申请日：2023-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Yang Sun ,  Guan-Wei Wu

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: A clock control circuit module, a memory storage device, and a clock control method are disclosed. The clock control circuit module is configured to: generate a clock signal; receive a first signal and the clock signal and sample the first signal according to the clock signal to generate a first sampling signal and a second sampling signal; obtain first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal respectively; and evaluate a frequency shift status between the first signal and the clock signal according to the first position information and the second position information.

公开(公告)号：US11206157B1

公开(公告)日：2021-12-21

申请号：US17067776

申请日：2020-10-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Zhen-Hong Hung ,  Sheng-Wen Chen ,  Shih-Yang Sun

IPC: H04L25/03 ,  H04L7/00

Abstract: A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.

公开(公告)号：US11636902B2

公开(公告)日：2023-04-25

申请号：US17468711

申请日：2021-09-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Guan-Wei Wu ,  Jen-Chu Wu ,  Jen-Huo Wang ,  Yu-Chiang Liao ,  Shih-Yang Sun

IPC: G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G11C29/10 ,  H01L27/20 ,  G11C29/12 ,  H04L27/20

Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

公开(公告)号：US10965438B1

公开(公告)日：2021-03-30

申请号：US16779666

申请日：2020-02-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Yang Sun ,  Sheng-Wen Chen ,  Yen-Po Lin ,  Bo-Jing Lin ,  Po-Min Cheng

IPC: H04L7/00 ,  H04L25/03 ,  H03L7/085 ,  H03L7/099

Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.