公开(公告)号：US11062781B1

公开(公告)日：2021-07-13

申请号：US16916137

申请日：2020-06-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Zhen-Hong Hung ,  Shih-Yang Sun ,  Sheng-Wen Chen

IPC: G11C16/32

Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.

公开(公告)号：US11206157B1

公开(公告)日：2021-12-21

申请号：US17067776

申请日：2020-10-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Zhen-Hong Hung ,  Sheng-Wen Chen ,  Shih-Yang Sun

IPC: H04L25/03 ,  H04L7/00

Abstract: A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.

公开(公告)号：US20210191453A1

公开(公告)日：2021-06-24

申请号：US16736819

申请日：2020-01-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Wen Chen ,  Shih-Yang Sun ,  Zhen-Hong Hung

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/12 ,  G11C11/4076 ,  G11C11/4074 ,  H03L7/08

Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.