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公开(公告)号：US10749728B1
公开(公告)日：2020-08-18
申请号：US16362725
申请日：2019-03-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.
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公开(公告)号：US09712175B2
公开(公告)日：2017-07-18
申请号：US15261878
申请日：2016-09-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen , Yu-Chiang Liao
CPC classification number: H03L7/091 , G11C7/1084 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0802 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/1072 , H03L7/22 , H04L7/0004 , H04L7/033
Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.
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公开(公告)号：US11636902B2
公开(公告)日：2023-04-25
申请号：US17468711
申请日：2021-09-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Guan-Wei Wu , Jen-Chu Wu , Jen-Huo Wang , Yu-Chiang Liao , Shih-Yang Sun
Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
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公开(公告)号：US20200252258A1
公开(公告)日：2020-08-06
申请号：US16362725
申请日：2019-03-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.
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公开(公告)号：US20210257033A1
公开(公告)日：2021-08-19
申请号：US16805848
申请日：2020-03-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Bo-Jing Lin , Yu-Chiang Liao
Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.
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Patent Agency Ranking
公开(公告)号：US09716506B2
公开(公告)日：2017-07-25
申请号：US15261877
申请日：2016-09-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen , Yu-Chiang Liao
CPC classification number: H03L7/091 , G11C7/1084 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0802 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/1072 , H03L7/22 , H04L7/0004 , H04L7/033
Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.
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公开(公告)号：US20170019116A1
公开(公告)日：2017-01-19
申请号：US15261878
申请日：2016-09-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen , Yu-Chiang Liao
IPC: H03L7/091
CPC classification number: H03L7/091 , G11C7/1084 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0802 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/1072 , H03L7/22 , H04L7/0004 , H04L7/033
Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.
Abstract translation: 提供时钟和数据恢复电路模块和锁相方法。 该模块包括相位检测电路，转换器电路和电压控制振荡电路。 相位检测电路被配置为检测数据信号和反馈时钟之间的相位差。 转换器电路耦合到相位检测电路，并被配置为根据相位差输出第一相位控制电压和第二相位控制电压。 电压控制振荡电路耦合到转换器电路，并被配置为接收第一相位控制电压和第二相位控制电压，并根据第一相位控制电压和第二相位控制电压输出反馈时钟。
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公开(公告)号：US20230048903A1
公开(公告)日：2023-02-16
申请号：US17468711
申请日：2021-09-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Guan-Wei Wu , Jen-Chu Wu , Jen-Huo Wang , Yu-Chiang Liao , Shih-Yang Sun
Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
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公开(公告)号：US11101003B1
公开(公告)日：2021-08-24
申请号：US16805848
申请日：2020-03-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Bo-Jing Lin , Yu-Chiang Liao
Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.
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公开(公告)号：US11075637B2
公开(公告)日：2021-07-27
申请号：US16702495
申请日：2019-12-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.
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