公开(公告)号：US08830750B1

公开(公告)日：2014-09-09

申请号：US13928356

申请日：2013-06-26

Applicant: Phison Electronics Corp.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Yu-Hsiang Lin ,  Shao-Wei Yen ,  Kuo-Hsin Lai

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括基于字线的存储器单元的临界电压分布来确定相应的读取电压。 该方法还包括：如果存储器单元的临界电压分布是右偏移分布，则将一组正确的调整读取电压施加到字线以读取多个位数据作为相应的软值; 并解码对应的软值以获得存储在存储单元中的页面数据。 这里，正确调整读取电压的集合包括多个正调整读取电压和多个负调整读取电压，并且正调整读取电压的数量大于负调整读取电压的数量。 因此，可以正确地识别存储器单元的存储状态。

公开(公告)号：US20140047160A1

公开(公告)日：2014-02-13

申请号：US13653424

申请日：2012-10-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kuo-Yi Cheng ,  Chun-Yen Chang

IPC: G06F12/02 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3468 ,  G11C16/3495 ,  G11C2211/5621

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method.

Abstract translation: 一种用于将数据写入可重写非易失性存储器模块的存储单元的数据写入方法，以及使用相同区域的存储器控​​制器和存储器存储装置。 该方法包括记录存储单元的磨损程度，并且基于其磨损程度调整对应于存储单元的初始写入电压和写入电压脉冲时间。 该方法还包括通过施加初始写入电压和写入电压脉冲时间对存储器单元进行编程，从而将数据写入存储单元。 因此，可以通过该方法将数据精确地存储到可重写非易失性存储器模块中。

公开(公告)号：US20130254629A1

公开(公告)日：2013-09-26

申请号：US13901239

申请日：2013-05-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Chih-Kang Yeh

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  H03M13/05 ,  H03M13/27

Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.

Abstract translation: 提供一种存储装置。 存储装置的控制器包括纠错模块和数据混乱模块。 纠错模块被配置为对要写入存储装置的闪速存储器模块的数据分组执行纠错过程，用于产生包含数据分组和对应的纠错码的序列数据代码，其中数据分组包括数据 要写入的区域记录数据和与数据分组相关的备用区域记录数据。 数据无序模块被配置为将序列数据代码转换为非序列数据代码，其中数据区域和备用区域的数据和纠错码分散在非序列数据代码中。 因此，可以有效地提高数据包的安全性。

公开(公告)号：US09136875B2

公开(公告)日：2015-09-15

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10 ,  H03M13/11

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US09019770B2

公开(公告)日：2015-04-28

申请号：US13901571

申请日：2013-05-24

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。

公开(公告)号：US20150067446A1

公开(公告)日：2015-03-05

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US20150006983A1

公开(公告)日：2015-01-01

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/50 ,  G11C16/26

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20140286105A1

公开(公告)日：2014-09-25

申请号：US13917621

申请日：2013-06-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/26 ,  H01L29/792

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。

公开(公告)号：US09437309B2

公开(公告)日：2016-09-06

申请号：US14943035

申请日：2015-11-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C11/00 ,  G11C16/14 ,  G11C16/26 ,  H01L29/792 ,  H01L27/115 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。

公开(公告)号：US20160078952A1

公开(公告)日：2016-03-17

申请号：US14943035

申请日：2015-11-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。