公开(公告)号：US09798228B2

公开(公告)日：2017-10-24

申请号：US14869416

申请日：2015-09-29

Applicant: NXP B.V.

Inventor： Hans Cobussen ,  Tonny Kamphuis ,  Heimo Scheucher ,  Laurentius de Kok

IPC: G03F1/44

CPC classification number: G03F1/44 ,  G03F9/7084 ,  H01L22/30 ,  H01L27/0203

Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.

公开(公告)号：US20170200646A1

公开(公告)日：2017-07-13

申请号：US14994590

申请日：2016-01-13

Applicant: NXP B.V.

Inventor： John Suman Nakka ,  Tonny Kamphuis ,  Roelf Anco Jacob Groenhuis

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/544 ,  H01L23/31 ,  H01L23/00 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/11

Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.

公开(公告)号：US20170025334A1

公开(公告)日：2017-01-26

申请号：US14806526

申请日：2015-07-22

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis ,  Rintje van der Meulen ,  Emil Casey Israel

IPC: H01L23/495 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

Abstract translation: 与示例性实施例一致，存在制备具有增强散热的集成电路（IC）装置的方法。 该方法包括提供具有第一厚度的引线框架阵列和多个管芯放置区域，每个管芯放置区域都具有接合焊盘着陆部分，所述焊接不良接地位于一侧或多侧上的管芯放置区域周围，接合焊盘着陆 具有上表面和相对的下表面，将具有第二厚度的至少两个第一厚度的安装突片的第二厚度的散热器组件放置在每个管芯放置区域中，并将所述至少两个安装突片附接到用作锚固件的相应接合焊盘平台上 衬垫，将器件裸片焊接在散热器器件组件上，将器件管芯接合焊盘导电地接合到相应的接合焊盘平台上，并将引线接合器件管芯，散热器组件和引线框架阵列封装在模制化合物中。

公开(公告)号：US20150069587A1

公开(公告)日：2015-03-12

申请号：US14514619

申请日：2014-10-15

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leonardus Antonius Elisabeth van Gemert ,  Caroline Catharina Maria Beelen-Hendrikx

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/60

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/3185 ,  H01L23/544 ,  H01L23/60 ,  H01L24/05 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract translation: 提出了在晶片级晶片（也称为晶片级芯片级封装，WLCSP）封装的集成电路及其制造方法。 WLCSP包括具有形成在管芯上表面上方的导电再分配层RDL的管芯，RDL限定信号路由电路。 该方法包括以下步骤：沉积导电RDL以便形成围绕信号路由电路的导电环; 并用导电屏蔽材料涂覆模具的侧表面和下表面。

公开(公告)号：US08895357B2

公开(公告)日：2014-11-25

申请号：US13857091

申请日：2013-04-04

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leonardus Antonius Elisabeth van Gemert ,  Caroline Catharina Maria Beelen-Hendrikx

IPC: H01L21/00 ,  H01L23/552 ,  H01L21/48 ,  H01L23/60 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/3185 ,  H01L23/544 ,  H01L23/60 ,  H01L24/05 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract translation: 提出了在晶片级晶片（也称为晶片级芯片级封装，WLCSP）封装的集成电路及其制造方法。 WLCSP包括具有形成在管芯上表面上方的导电再分配层RDL的管芯，RDL限定信号路由电路。 该方法包括以下步骤：沉积导电RDL以便形成围绕信号路由电路的导电环; 并用导电屏蔽材料涂覆模具的侧表面和下表面。

公开(公告)号：US10109564B2

公开(公告)日：2018-10-23

申请号：US15431124

申请日：2017-02-13

Applicant: NXP B.V.

Inventor： Roelf Groenhuis ,  Leo Van Gemert ,  Tonny Kamphuis ,  Jan Gulpen

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

公开(公告)号：US09953903B2

公开(公告)日：2018-04-24

申请号：US14806526

申请日：2015-07-22

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis ,  Rintje van der Meulen ,  Emil Casey Israel

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/433 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

公开(公告)号：US20170179076A1

公开(公告)日：2017-06-22

申请号：US15450972

申请日：2017-03-06

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leonardus Antonius Elisabeth van Gemert ,  Roelf Anco Jacob Groenhuis ,  Caroline Catharina Maria Beelen-Hendrikx ,  Jetse de Witte ,  Franciscus Henrikus Martinus Swartjes

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3164 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/11 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

公开(公告)号：US20170148697A1

公开(公告)日：2017-05-25

申请号：US15342285

申请日：2016-11-03

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leo van Gemert ,  Hans van Rijckevorsel ,  Sascha Moeller ,  Hartmut Buenning ,  Steffen Holland ,  Y Kuang Huang

IPC: H01L23/31 ,  H01L29/06 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/683 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/32051 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/528 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10156 ,  H01L2924/17747 ,  H01L2924/35 ,  H01L2924/37

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

公开(公告)号：US20170103939A1

公开(公告)日：2017-04-13

申请号：US14880076

申请日：2015-10-09

Applicant: NXP B.V.

Inventor： Jan Gulpen ,  Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/4951 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead frame having I/O terminals surrounding a die attach region, the lead frame defined onto a temporary carrier. A device die is attached onto the die-attach region. The device die is wire bonded to the I/O terminals, the I/O terminals located in a first position. In a molding compound the wire-bonded device die and lead frame are encapsulated. The temporary carrier is removed from the lead frame, underside surfaces of the device die and I/O terminals are exposed. Applying a non-conductive layer to the exposed underside surfaces of the device die and I/O terminals, thereby defines features in which conductive traces may be defined from the I/O terminals in the first position to customized I/O terminals located in a second position.