公开(公告)号：US20150364549A1

公开(公告)日：2015-12-17

申请号：US14301348

申请日：2014-06-11

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Lee ,  Ming-Tzong Yang ,  Wei-Che Huang ,  Cheng-Chou Hung

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiC device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiC.

Abstract translation: 具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 在所述内部区域中的所述半导体衬底上的SiC器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。 至少一个虚拟图案包含SiC。

公开(公告)号：US09190976B2

公开(公告)日：2015-11-17

申请号：US13804206

申请日：2013-03-14

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00 ,  H01P1/203 ,  H01P7/08

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.

Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件以及形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。

公开(公告)号：US20130265121A1

公开(公告)日：2013-10-10

申请号：US13804206

申请日：2013-03-14

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.

Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件和形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。

公开(公告)号：US09859356B2

公开(公告)日：2018-01-02

申请号：US15044121

申请日：2016-02-16

Applicant: MEDIATEK INC.

Inventor： Ming-Da Tsai ,  Tao-Yi Lee ,  Cheng-Chou Hung ,  Tung-Hsing Lee

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227

Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

公开(公告)号：US09620580B2

公开(公告)日：2017-04-11

申请号：US14284199

申请日：2014-05-21

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Cheng-Chou Hung

IPC: H01L27/01 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/02181 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08123 ,  H01L2224/08265 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85007 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19051 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

公开(公告)号：US09543377B2

公开(公告)日：2017-01-10

申请号：US14548298

申请日：2014-11-20

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L23/60 ,  H01L29/788 ,  H01L29/06 ,  H01L29/74 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

公开(公告)号：US20160351653A1

公开(公告)日：2016-12-01

申请号：US15044121

申请日：2016-02-16

Applicant: MEDIATEK INC.

Inventor： Ming-Da Tsai ,  Tao-Yi Lee ,  Cheng-Chou Hung ,  Tung-Hsing Lee

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L28/10 ,  H01L23/5227

Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

Abstract translation: 半导体集成电路包括电感器和多个高磁导率图案。 电感器包括一个导电回路。 高导磁率图案设置在导电环路附近。

公开(公告)号：US20160148992A1

公开(公告)日：2016-05-26

申请号：US14548298

申请日：2014-11-20

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L29/06 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

公开(公告)号：US08987851B2

公开(公告)日：2015-03-24

申请号：US13790060

申请日：2013-03-08

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L27/14 ,  H01L29/40 ,  H01L21/76 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.

Abstract translation: 本发明提供一种射频（RF）器件封装及其制造方法。 射频（RF）器件封装的示例性实施例包括基座，其中射频（RF）器件芯片安装在基座上。 RF器件芯片包括具有前侧和后侧的半导体衬底。 射频（RF）部件设置在半导体衬底的前侧。 互连结构设置在RF部件上，其中互连结构电连接到RF部件，并且半导体衬底的厚度小于互连结构的厚度。 从半导体衬底的背面穿过半导体衬底形成一个通孔，并连接到互连结构。 TSV结构设置在通孔中。

公开(公告)号：US20140035096A1

公开(公告)日：2014-02-06

申请号：US13797992

申请日：2013-03-12

Applicant: MEDIATEK INC.

Inventor： Ming-Da Tsai ,  George Chien ,  Cheng-Chou Hung

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/20

Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.

Abstract translation: 一种用于在集成部件的制造期间控制无源器件的电性能的方法包括提供衬底，在衬底上制造无源器件，测量无源器件的电性能以获得测量结果，确定至少一个布局 通过用于调整无源器件的电性能的测量结果对应于至少一个后续制造过程的模式，以及继续包括集成部件的至少一个后续制造过程的其余的制造。