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    Integrated circuit apparatus
    2.
    发明授权
    Integrated circuit apparatus 有权

    公开(公告)号：US10068856B2

    公开(公告)日：2018-09-04

    申请号：US15609039

    申请日：2017-05-31

    Applicant: MEDIATEK INC.

    Inventor： Jui-Chih Kao ,  Ming-Da Tsai ,  Yuan-Yu Fu ,  Chih-Chun Hsu

    IPC: H01L23/552 ,  H01L23/58 ,  H01L23/64

    Abstract: An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.

    LOW NOISE AMPLIFIER AND SAW-LESS RECEIVER WITH LOW-NOISE AMPLIFIER
    4.
    发明申请
    LOW NOISE AMPLIFIER AND SAW-LESS RECEIVER WITH LOW-NOISE AMPLIFIER 有权
    低噪声放大器和低噪声放大器的无噪声接收器

    公开(公告)号：US20130314160A1

    公开(公告)日：2013-11-28

    申请号：US13798097

    申请日：2013-03-13

    Applicant: MEDIATEK INC.

    Inventor： Ming-Da Tsai ,  Chih-Fan Liao

    IPC: H03F3/193

    CPC classification number: H03F3/193 ,  H03F1/3211 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/294 ,  H03F2203/45138 ,  H03G3/3052 ,  H04B1/109

    Abstract: A low noise amplifier is used to amplify a differential input pair to generate a differential output pair. The low noise amplifier includes two main paths, two assistant circuits and two adders to make noise carried on two output signals of the differential output pair be the same; therefore, the noise of the two output signals can be fully cancelled in the following operations.

    Abstract translation: 低噪声放大器用于放大差分输入对以产生差分输出对。 低噪声放大器包括两个主路径，两个辅助电路和两个加法器，使差分输出对的两个输出信号上承载的噪声相同; 因此，在以下操作中可以完全取消两个输出信号的噪声。

    FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL
    5.
    发明申请
    FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL 有权
    用于产生输入时钟信号的频率分配器，其占用周期不同于输入时钟信号的占空比

    公开(公告)号：US20130043913A1

    公开(公告)日：2013-02-21

    申请号：US13658809

    申请日：2012-10-23

    Applicant: MEDIATEK INC.

    Inventor： Ming-Da Tsai

    IPC: H03K21/00

    CPC classification number: H03K23/425 ,  G06F1/08 ,  H03K3/356173 ,  H03K21/023 ,  H03K21/10

    Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.

    Abstract translation: 分频器包括多个逻辑电路块。 每个逻辑电路块具有多个控制端子。 一个逻辑电路块的控制端中的至少一个被布置成接收具有第一占空比的输入时钟信号。 逻辑电路块中的一个的剩余控制端中的至少一个被布置成通过正反馈耦合另一个逻辑电路块。 所述剩余控制端中的至少一个的时钟信号具有与第一占空比不同的第二占空比。 每个逻辑电路块包括并联在第一参考电压和输出端之间的多个第一晶体管，以及串联耦合在第二参考电压和输出端之间的多个第二晶体管。

    Phase synchronized LO generation
    6.
    发明授权
    Phase synchronized LO generation 有权

    公开(公告)号：US11640184B2

    公开(公告)日：2023-05-02

    申请号：US16918601

    申请日：2020-07-01

    Applicant: MEDIATEK INC.

    Inventor： Chien-Wei Tseng ,  Mohammed Fathey Abdelfattah Hassan ,  Li-Shin Lai ,  Tzu-Yu Yeh ,  Ming-Da Tsai ,  Bernard Mark Tenbroek

    IPC: G06F1/12 ,  G06F1/10 ,  H03K3/037

    Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

    Phase-rotated harmonic-rejection mixer apparatus
    7.
    发明授权
    Phase-rotated harmonic-rejection mixer apparatus 有权

    公开(公告)号：US10171034B2

    公开(公告)日：2019-01-01

    申请号：US15462923

    申请日：2017-03-20

    Applicant: MEDIATEK INC.

    Inventor： Chien-Wei Tseng ,  Ian Tseng ,  Ming-Da Tsai ,  Yangjian Chen ,  Chien-Cheng Lin

    IPC: H03D7/12 ,  H03D7/16

    Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

    Phased-array transceiver for millimeter-wave frequencies
    10.
    发明授权
    Phased-array transceiver for millimeter-wave frequencies 有权
    用于毫米波频率的相控阵收发器

    公开(公告)号：US09257746B2

    公开(公告)日：2016-02-09

    申请号：US14136898

    申请日：2013-12-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MediaTek, Inc.

    Inventor： Ping-Yu Chen ,  Brian A. Floyd ,  Jie-Wei Lai ,  Arun S. Natarajan ,  Sean T. Nicolson ,  Scott K. Reynolds ,  Ming-Da Tsai ,  Alberto Valdes-Garcia ,  Jing-Hong C. Zhan

    IPC: H01Q3/26

    CPC classification number: H01Q3/2694 ,  H01Q3/267

    Abstract: A phased-array receiver that may be effectively implemented on a silicon substrate. A receiver includes multiple radio frequency (RF) front-ends, each configured to receive a signal with a given delay relative to the others such that the gain of the received signal is highest in a given direction. The receiver also includes a power combination network configured to accept an RF signal from each of the RF front-ends and to pass a combined RF signal to a down-conversion element, where the power distribution network includes a combination of active and passive components. Each RF front-end includes a phase shifter configured to delay the signal in accordance with the given direction and a variable amplifier configured to adjust the gain of the signal.

    Abstract translation: 可以有效地在硅衬底上实现的相控阵接收器。 接收机包括多个射频（RF）前端，每个被配置为接收相对于其它的给定延迟的信号，使得接收信号的增益在给定方向上最高。 接收机还包括配置成接收来自每个RF前端的RF信号并将组合的RF信号传递到下变频元件的功率组合网络，其中配电网络包括有源和无源组件的组合。 每个RF前端包括被配置为根据给定方向延迟信号的移相器和配置成调整信号增益的可变放大器。

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