-
公开(公告)号：US20170207758A1
公开(公告)日：2017-07-20
申请号：US15348956
申请日：2016-11-10
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ming-Da Tsai
CPC classification number: H03F3/21 , H03F1/0266 , H03F1/14 , H03F1/3205 , H03F1/3276 , H03F3/193 , H03F2200/213 , H03F2200/222 , H03F2200/228 , H03F2200/435 , H03F2200/451 , H03F2200/465 , H03F2200/471 , H03F2200/546 , H03F2200/555 , H03F2200/75 , H03F2200/78 , H03F2201/3215
Abstract: A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.
-
公开(公告)号：US20170294878A1
公开(公告)日：2017-10-12
申请号：US15462923
申请日：2017-03-20
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ian Tseng , Ming-Da Tsai , Yangjian Chen , Chien-Cheng Lin
IPC: H03D7/12
CPC classification number: H03D7/12 , H03D7/165 , H03D2200/0082
Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.
-
Patent Agency Ranking
公开(公告)号：US20170214369A1
公开(公告)日：2017-07-27
申请号：US15361468
申请日：2016-11-27
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ming-Da Tsai
CPC classification number: H03F1/26 , H03F1/0261 , H03F1/301 , H03F3/193 , H03F3/195 , H03F3/21 , H03F3/245 , H03F3/45071 , H03F3/45085 , H03F3/45179 , H03F3/45183 , H03F2200/219 , H03F2200/225 , H03F2203/45144 , H03F2203/45154 , H03F2203/45172 , H03F2203/45542 , H03F2203/45621 , H03F2203/50
Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.
-
公开(公告)号：US10056869B2
公开(公告)日：2018-08-21
申请号：US15348956
申请日：2016-11-10
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ming-Da Tsai
CPC classification number: H03F3/21 , H03F1/0266 , H03F1/14 , H03F1/3205 , H03F1/3276 , H03F3/193 , H03F2200/213 , H03F2200/222 , H03F2200/228 , H03F2200/435 , H03F2200/451 , H03F2200/465 , H03F2200/471 , H03F2200/546 , H03F2200/555 , H03F2200/75 , H03F2200/78 , H03F2201/3215
Abstract: A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.
-
公开(公告)号：US11640184B2
公开(公告)日：2023-05-02
申请号：US16918601
申请日：2020-07-01
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Mohammed Fathey Abdelfattah Hassan , Li-Shin Lai , Tzu-Yu Yeh , Ming-Da Tsai , Bernard Mark Tenbroek
Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.
-
公开(公告)号：US10171034B2
公开(公告)日：2019-01-01
申请号：US15462923
申请日：2017-03-20
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ian Tseng , Ming-Da Tsai , Yangjian Chen , Chien-Cheng Lin
Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.
-
公开(公告)号：US10103691B2
公开(公告)日：2018-10-16
申请号：US15361468
申请日：2016-11-27
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Tseng , Ming-Da Tsai
Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.
-
-
-
-
-
-
Search Results
7
records
(took 0.013 seconds)
