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公开(公告)号：US20200052114A1
公开(公告)日：2020-02-13
申请号：US16600701
申请日：2019-10-14
发明人： Kangguo CHENG , SHOGO MOCHIZUKI , Choonghyun LEE , Juntao LI
IPC分类号： H01L29/78 , H01L21/02 , H01L29/06 , H01L27/088 , H01L29/66 , H01L29/10 , H01L21/8234 , H01L29/08 , H01L21/306 , H01L21/3065
摘要： Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.
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公开(公告)号：US20180294354A1
公开(公告)日：2018-10-11
申请号：US16006905
申请日：2018-06-13
IPC分类号： H01L29/78 , H01L29/08 , H01L29/167 , H01L21/02 , H01L21/306 , H01L29/66
摘要： Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
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公开(公告)号：US20180122937A1
公开(公告)日：2018-05-03
申请号：US15674697
申请日：2017-08-11
IPC分类号： H01L29/78 , H01L29/08 , H01L29/167 , H01L21/02 , H01L21/306 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/02532 , H01L21/02595 , H01L21/02598 , H01L21/30604 , H01L29/0847 , H01L29/167 , H01L29/66666 , H01L29/785
摘要： Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
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公开(公告)号：US20150295065A1
公开(公告)日：2015-10-15
申请号：US14752095
申请日：2015-06-26
发明人： HONG HE , SHOGO MOCHIZUKI , CHIAHSUN TSENG , CHUN-CHEN YEH , YUNPENG YIN
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/306 , H01L29/04 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/02271 , H01L21/0257 , H01L21/30604 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/045 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.
摘要翻译： 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。
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公开(公告)号：US20210273063A1
公开(公告)日：2021-09-02
申请号：US16805744
申请日：2020-02-29
发明人： Heng Wu , Ruilong Xie , SHOGO MOCHIZUKI , Lan Yu
IPC分类号： H01L29/417 , H01L29/66 , H01L29/08 , H01L29/10 , H01L21/311 , H01L29/45 , H01L21/8238 , H01L27/092 , H01L29/78
摘要： Improved top source and drain contact designs for VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: depositing a first ILD over a VTFET structure having fins patterned in a substrate, bottom source and drains at a base of the fins, bottom spacers on the bottom source and drains and gates alongside the fins; patterning trenches in the first ILD; forming top spacers lining the trenches; forming top source and drains in the trenches at the tops of the fins; forming sacrificial caps covering the top source and drains; depositing a second ILD onto the first ILD; patterning contact trenches in the second ILD, exposing the sacrificial caps; removing the sacrificial caps through the contact trenches; and forming top source and drain contacts in the contact trenches that wrap around the top source and drains. A VTFET device is also provided.
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16.发明申请公开(公告)号：US20200161451A1
公开(公告)日：2020-05-21
申请号：US16191549
申请日：2018-11-15
IPC分类号： H01L29/66 , H01L29/06 , H01L29/04 , H01L29/08 , H01L29/16 , H01L29/423 , H01L29/49 , H01L29/786
摘要： A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
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公开(公告)号：US20180190794A1
公开(公告)日：2018-07-05
申请号：US15897706
申请日：2018-02-15
IPC分类号： H01L29/66 , H01L21/311
CPC分类号： H01L29/66666 , H01L21/31111 , H01L29/0847 , H01L29/6653 , H01L29/6656 , H01L29/66795
摘要： A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.
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公开(公告)号：US20170033104A1
公开(公告)日：2017-02-02
申请号：US15292768
申请日：2016-10-13
发明人： HONG HE , SHOGO MOCHIZUKI , CHIAHSUN TSENG , CHUN-CHEN YEH , YUNPENG YIN
IPC分类号： H01L27/088 , H01L29/06 , H01L29/66 , H01L21/02 , H01L21/8234 , H01L29/04 , H01L29/08
CPC分类号： H01L27/0886 , H01L21/02271 , H01L21/0257 , H01L21/30604 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/045 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.
摘要翻译： 半导体器件包括在绝缘体层中的沟槽中形成的多个散热片。 多个翅片中的每一个具有均匀的晶体取向和在垂直和横向延伸超过沟槽的源极和漏极区域中的鳍帽。 各个翅片的翅片帽彼此分开。 栅极结构形成在使源极和漏极区域露出的鳍片之上。 绝缘体层至少部分地覆盖栅极结构的侧壁。
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19.发明申请METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION 有权形成外延缓冲层的方法，用于FINFET源和漏极连接漏电减少公开(公告)号：US20160284701A1
公开(公告)日：2016-09-29
申请号：US15170299
申请日：2016-06-01
发明人： DECHAO GUO , SHOGO MOCHIZUKI , ANDREAS SCHOLZE , CHUN-CHEN YEH
IPC分类号： H01L27/088 , H01L29/66 , H01L29/08 , H01L21/8234 , H01L29/165 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/2252 , H01L21/324 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/08 , H01L29/0843 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/66545 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
摘要翻译： 一种半导体器件，其包括鳍结构的沟道区域上的栅极结构，以及鳍状结构的源极区域和漏极区域上的外延源区域和外延漏极区域中的至少一个。 外延源区部分和外延漏区部分中的至少一个包括与鳍结构相邻的第一浓度掺杂部分和第一浓度掺杂部分上的第二浓度掺杂部分。 第二浓度部分具有比第一浓度掺杂部分更大的掺杂剂浓度。 扩展掺杂剂区域延伸到鳍结构的沟道部分，其具有每十年或更长时间为7nm的n型或p型掺杂剂的突变掺杂剂浓度梯度。
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公开(公告)号：US20150194504A1
公开(公告)日：2015-07-09
申请号：US14666464
申请日：2015-03-24
发明人： HONG HE , SHOGO MOCHIZUKI , CHIAHSUN TSENG , CHUN-CHEN YEH , YUNPENG YIN
IPC分类号： H01L29/66
CPC分类号： H01L27/0886 , H01L21/02271 , H01L21/0257 , H01L21/30604 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/045 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.
摘要翻译： 用于形成具有非合并翅片延伸部分的半导体器件的方法。 用于形成半导体器件的方法包括在衬底的绝缘体层中形成沟槽。 鳍形成在沟槽中，并且虚拟栅极形成在鳍上，留下源极和漏极区域暴露。 翅片被蚀刻在周围绝缘体层的表面水平之下。 翅片延伸部从蚀刻的翅片外延生长。
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