公开(公告)号：US09917021B2

公开(公告)日：2018-03-13

申请号：US15363420

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC: H01L21/8238 ,  H01L21/36 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167 ,  H01L21/326 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/326 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/7849 ,  H01L29/785

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US20170229538A1

公开(公告)日：2017-08-10

申请号：US15207802

申请日：2016-07-12

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

公开(公告)号：US20170076999A1

公开(公告)日：2017-03-16

申请号：US15363420

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/326 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/7849 ,  H01L29/785

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US09455314B1

公开(公告)日：2016-09-27

申请号：US15016839

申请日：2016-02-05

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0638 ,  H01L21/2255 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor structure is provided that includes at least one punch-through stop base structure having concave outermost sidewalls and located on a semiconductor surface of a semiconductor substrate. The structure further includes a pair of semiconductor fins extending upwards from a topmost surface of the at least one punch through stop base structure. The structure even further includes a trench isolation structure located laterally adjacent each of the concave outermost sidewalls of the at least one punch-through stop base structure, wherein a dopant source dielectric material liner is located on each of the concave outermost sidewalls of the at least one punch-through stop base structure and is present between the at least one punch-through stop base structure and the trench isolation structure.

Abstract translation: 提供一种半导体结构，其包括至少一个具有凹入的最外侧壁并位于半导体衬底的半导体表面上的穿通止动器基座结构。 该结构还包括从至少一个冲头的最上表面向上延伸通过止动基座结构的一对半导体翅片。 所述结构甚至还包括沟槽隔离结构，该沟槽隔离结构位于横向邻近所述至少一个穿通止动器基座结构的所述凹入的最外侧壁中，其中掺杂剂源电介质材料衬垫位于所述至少一个穿通止动器基底结构的每个所述凹入的最外侧壁 一个穿通止动基座结构，并且存在于该至少一个穿通止动器基座结构和沟槽隔离结构之间。

公开(公告)号：US09245892B2

公开(公告)日：2016-01-26

申请号：US14184756

申请日：2014-02-20

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Pooja R. Batra ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L27/10867 ,  H01L21/743 ,  H01L21/7687 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/66181 ,  H01L29/785 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

Abstract translation: 本发明的实施例提供一种半导体器件及其制造方法。 在本发明的实施例中，半导体结构包括水平地形成在半导体衬底上的第一导体。 第二导体垂直地形成在包括半导体衬底的半导体堆叠中。 在第一导体附近形成氧化区域。 第二导体以与第一导体电连通的方式形成。 第一导体以横向连接到第二导体的方式形成。 第一导体以不会在氧化区域下方穿过的方式形成。 第一导体以与包括在半导体结构中的相邻外延材料具有降低的连接电阻的方式形成。

公开(公告)号：US20150333156A1

公开(公告)日：2015-11-19

申请号：US14808914

申请日：2015-07-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

公开(公告)号：US09029913B2

公开(公告)日：2015-05-12

申请号：US13792291

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Huiling Shang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795

Abstract: A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.

Abstract translation: 在包括硅的半导体衬底上形成第一硅锗合金层。 在第一硅 - 锗合金层的第一区域上形成第一硅层和第二硅 - 锗合金层的堆叠，并且在第一硅 - 锗合金层的第二区域上形成比第一硅层厚的第二硅层 硅锗合金层。 在第一区域中形成至少一个第一半导体鳍片，并且在第二区域中形成至少一个第二半导体鳍片。 去除第一硅层的剩余部分以在第一区域中提供至少一个硅 - 锗合金翅片，而在第二区域中提供至少一个硅片。 鳍状场效应晶体管可以形成在至少一个硅 - 锗合金翅片和至少一个硅片上。

公开(公告)号：US08987823B2

公开(公告)日：2015-03-24

申请号：US13771255

申请日：2013-02-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim ,  Ramachandra Divakaruni

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。 还公开了包括体型翅片，SOI型翅片和平面区域的结构。

公开(公告)号：US08928086B2

公开(公告)日：2015-01-06

申请号：US13737089

申请日：2013-01-09

Applicant: International Business Machines Corporation

Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

公开(公告)号：US10559662B2

公开(公告)日：2020-02-11

申请号：US15467821

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L29/161 ,  H01L29/04

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.