公开(公告)号：US08629003B2

公开(公告)日：2014-01-14

申请号：US13859005

申请日：2013-04-09

Applicant: General Electric Company

Inventor： Thomas Bert Gorczyca ,  Paul Alan McConnelee

IPC: H01L21/02 ,  C08J7/18 ,  B05D3/02

CPC classification number: H01L23/28 ,  C08G59/50 ,  C08K5/1515 ,  C08K5/1539 ,  C08K5/17 ,  C08K5/18 ,  C09J163/00 ,  H01L21/56 ,  H01L23/293 ,  H01L2224/48091 ,  H01L2224/92144

Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

Abstract translation: 粘合剂包括环氧树脂和硬化剂。 硬化剂包括三氧二胺，二氨基二环己基甲烷，甲苯二胺和双酚A二酐。

公开(公告)号：US20130214435A1

公开(公告)日：2013-08-22

申请号：US13859005

申请日：2013-04-09

Applicant: General Electric Company

Inventor： Thomas Bert Gorczyca ,  Paul Alan McConnelee

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  C08G59/50 ,  C08K5/1515 ,  C08K5/1539 ,  C08K5/17 ,  C08K5/18 ,  C09J163/00 ,  H01L21/56 ,  H01L23/293 ,  H01L2224/48091 ,  H01L2224/92144

Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

Abstract translation: 粘合剂包括环氧树脂和硬化剂。 硬化剂包括三氧二胺，二氨基二环己基甲烷，甲苯二胺和双酚A二酐。

公开(公告)号：US10269688B2

公开(公告)日：2019-04-23

申请号：US13897685

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

公开(公告)号：US10186477B2

公开(公告)日：2019-01-22

申请号：US15363237

申请日：2016-11-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

公开(公告)号：US20180082857A1

公开(公告)日：2018-03-22

申请号：US15827199

申请日：2017-11-30

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US09806051B2

公开(公告)日：2017-10-31

申请号：US14195930

申请日：2014-03-04

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L24/32 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/2711 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/80365 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/207 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/305 ,  H05K3/306 ,  H05K3/366 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/302 ,  Y02P70/613

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US09704788B2

公开(公告)日：2017-07-11

申请号：US14665735

申请日：2015-03-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

公开(公告)号：US09679837B2

公开(公告)日：2017-06-13

申请号：US15082501

申请日：2016-03-28

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L29/40 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: An electrical interconnect assembly includes an insulating substrate, upper conductive pads coupled to a top surface of the insulating substrate, and lower conductive pads coupled to a bottom surface of the insulating substrate. The upper conductive pads and the lower conductive pads comprise an electrically conductive material. A metallization layer is deposited on the top surface of the insulating substrate and the upper conductive pads. The metallization layer extends through vias formed through a thickness of the insulating substrate to contact a top surface of the lower conductive pads.

公开(公告)号：US09653438B2

公开(公告)日：2017-05-16

申请号：US14464877

申请日：2014-08-21

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L29/74 ,  H01L31/111 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.

公开(公告)号：US09236348B2

公开(公告)日：2016-01-12

申请号：US14188093

申请日：2014-02-24

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Scott Smith ,  Elizabeth Ann Burke

IPC: H01L23/12 ,  H01L21/00 ,  H05K1/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H05K1/18 ,  H01L23/522 ,  H01L23/48 ,  H01L21/48 ,  H05K3/46 ,  H01L25/10 ,  H01L21/60

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2021/60 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/144 ,  H05K1/185 ,  H05K1/189 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4673 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die.

Abstract translation: 形成掩埋模具模块的方法包括提供初始层叠柔性层并通过初始层压柔性层形成模具开口。 第一未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第一表面，并且模具定位在初始层压柔性层的模具开口内并粘附到粘合剂材料上。 第二未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第二表面上，然后固化粘合剂材料。 在第一和第二未切割的层叠柔性层中和第二未切割的层叠柔性层上形成通孔和金属互连，其中每个金属互连件延伸通过相应的通孔，并且直接金属化到初始层压柔性层上的金属互连或模具上的管芯焊盘 。