公开(公告)号：US12046473B2

公开(公告)日：2024-07-23

申请号：US17358244

申请日：2021-06-25

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Vittoriano Ruscio ,  Wei Zou ,  David J. Lee

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L21/265 ,  H01L21/26593 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US11804537B2

公开(公告)日：2023-10-31

申请号：US17307809

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Hans-Joachim L. Gossmann

IPC: H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66068 ,  H01L21/047 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7813

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

公开(公告)号：US11728214B2

公开(公告)日：2023-08-15

申请号：US17341080

申请日：2021-06-07

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76859 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/535 ,  H01L23/53257 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40

Abstract: A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

公开(公告)号：US11699570B1

公开(公告)日：2023-07-11

申请号：US17665970

申请日：2022-02-07

Applicant: Applied Materials, Inc.

Inventor： Supakit Charnvanichborikarn ,  Wei Zou ,  Hans-Joachim L. Gossmann ,  Qintao Zhang ,  Aseem Kumar Srivastava ,  William Robert Bogiages, Jr. ,  Wei Zhao

IPC: H01J37/317 ,  H01J37/304

CPC classification number: H01J37/3171 ,  H01J37/304 ,  H01J2237/31705

Abstract: A method of performing an ion implantation process using a beam-line ion implanter, including disposing a substrate on a platen, analyzing the substrate using metrology components, communicating data relating to the analysis of the substrate to a feedforward controller, processing the data using a predictive model executed by the feedforward controller to compensate for variations in the substrate and to compensate for variations in components of the beam-line ion implanter based on historical data collected from previous implantation operations, and using output from the predictive model to adjust operational parameters of the beam-line ion implanter.

公开(公告)号：US20220392804A1

公开(公告)日：2022-12-08

申请号：US17341080

申请日：2021-06-07

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/06 ,  H01L49/02

Abstract: A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

公开(公告)号：US12087585B2

公开(公告)日：2024-09-10

申请号：US17362946

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Judy Campbell Soukup

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/26593 ,  H01L21/26533 ,  H01L21/266

Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

公开(公告)号：US11721743B2

公开(公告)日：2023-08-08

申请号：US17130605

申请日：2020-12-22

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou ,  Samphy Hong

IPC: H01L29/66 ,  H01L21/67 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/67069 ,  H01L21/67075 ,  H01L29/66431 ,  H01L29/66636 ,  H01L29/778

Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

公开(公告)号：US20230178373A1

公开(公告)日：2023-06-08

申请号：US17541459

申请日：2021-12-03

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou

IPC: H01L21/266 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L21/266 ,  H01L21/0465 ,  H01L29/1608

Abstract: Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.

公开(公告)号：US11527412B2

公开(公告)日：2022-12-13

申请号：US17113073

申请日：2020-12-06

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Felix Levitov ,  Lei Zhong ,  Wei Zou

IPC: H01L21/311 ,  H01J37/317 ,  H01L21/3115

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

公开(公告)号：US20220359723A1

公开(公告)日：2022-11-10

申请号：US17873380

申请日：2022-07-26

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3215

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.