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    FLAT PANEL DETECTOR
    11.
    发明申请
    FLAT PANEL DETECTOR 失效
    平板检测器

    公开(公告)号：US20080035852A1

    公开(公告)日：2008-02-14

    申请号：US11833652

    申请日：2007-08-03

    Applicant: Yasushi Nagata ,  Takehiko Shoji ,  Masashi Kondo ,  Mitsuru Sekiguchi

    Inventor： Yasushi Nagata ,  Takehiko Shoji ,  Masashi Kondo ,  Mitsuru Sekiguchi

    IPC: G01T1/20

    CPC classification number: G01T1/2002

    Abstract: An objective is to provide a radiation flat panel detector in which degradation of a phosphor layer property during aging is inhibited, the phosphor layer is protected from chemical alteration and physical impact, and sharpness is excellent. Also disclosed is a flat panel detector possessing a light-receiving element and provided thereon, a scintillator panel possessing a scintillator sheet having a phosphor layer provided on a substrate and provided thereon, a first protective film placed on the phosphor layer side and a second protective film placed on the substrate side to seal the scintillator sheet, wherein the light-receiving element is provided on the first protective film side of the scintillator panel; and the scintillator sheet is sealed at 5-8000 Pa.

    Abstract translation: 目的是提供一种辐射平板检测器，其中抑制了老化期间荧光体层性质的劣化，防止了荧光体层的化学变化和物理冲击，并且清晰度优异。 还公开了一种具有光接收元件并设置在其上的平板检测器，具有闪烁体片的闪烁体面板，其具有设置在基板上的磷光体层，设置在其上的第一保护膜，位于荧光体层侧，第二保护膜 薄膜放置在基板侧以密封闪烁体片，其中光接收元件设置在闪烁体面板的第一保护膜侧上; 闪烁片在5-8000Pa下密封。

    Semiconductor device and method for fabricating the same
    13.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US06534868B2

    公开(公告)日：2003-03-18

    申请号：US09986289

    申请日：2001-11-08

    Applicant: Mitsuru Sekiguchi

    Inventor： Mitsuru Sekiguchi

    IPC: H01L2348

    CPC classification number: H01L21/76885 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

    Method for fabricating semiconductor device
    14.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6150248A

    公开(公告)日：2000-11-21

    申请号：US102383

    申请日：1998-06-22

    Applicant: Mitsuru Sekiguchi ,  Shinichi Ogawa ,  Kikuko Tsutsumi ,  Tatsuo Sugiyama

    Inventor： Mitsuru Sekiguchi ,  Shinichi Ogawa ,  Kikuko Tsutsumi ,  Tatsuo Sugiyama

    IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/44

    CPC classification number: H01L21/28518

    Abstract: A method for fabricating a semiconductor device including a silicon region and a cobalt silicide film, the cobalt silicide film being in contact with at least a part of the silicon region. The method includes the steps of: doping at least part of the silicon region with boron by setting a doping level of boron in the part at 1.times.10.sup.15 cm.sup.-3 or more; depositing a cobalt film over a surface of the silicon region; conducting a first heat treatment for producing a silicidation reaction in a contact region between the cobalt film and the silicon region and thereby forming the cobalt silicide film; selectively removing unreacted portions of the cobalt film that have not been turned into silicide; and conducting a second heat treatment at a temperature higher than a temperature set for the first heat treatment step, thereby inducing a phase transition in the cobalt silicide film. The first heat treatment step is performed within a reducing ambient gas, and the temperature set for the first heat treatment step is in the range from about 400.degree. C. to about 600.degree. C., both inclusive.

    Abstract translation: 一种制造包括硅区和硅化钴膜的半导体器件的方法，所述钴硅化物膜与所述硅区的至少一部分接触。 该方法包括以下步骤：通过在1×10 15 cm -3以上设定该部分中的硼的掺杂水平，用硼掺杂至少一部分硅区域; 在所述硅区域的表面上沉积钴膜; 进行第一热处理，以在钴膜和硅区域之间的接触区域中产生硅化反应，从而形成硅化钴膜; 选择性地除去尚未变成硅化物的钴膜的未反应部分; 并在比第一热处理步骤设定的温度高的温度下进行第二次热处理，从而引起硅化钴膜的相变。 第一热处理步骤在还原环境气体中进行，并且第一热处理步骤设定的温度在约400℃至约600℃的范围内。

    Non-volatile semiconductor memory device
    16.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5936891A

    公开(公告)日：1999-08-10

    申请号：US120742

    申请日：1998-07-23

    Applicant: Mitsuru Sekiguchi

    Inventor： Mitsuru Sekiguchi

    IPC: G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  G11C7/00

    CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/30 ,  G11C16/344 ,  G11C2216/18

    Abstract: It is an object of the invention to provided an electrically erasable and programmable non-volatile semiconductor memory device, in which misread of a datum stored in a memory cell can be avoided by suppressing floating of the potentials of a memory cell source wire and a word wire in case that the operation of the memory device shifts from erasing pulse application to erase verify. Two transistors with different current-driving capabilities are connected in parallel and inserted between the memory cell source wire and the ground plane. When the operation of the memory device shifts from erasing pulse application to erase verify, a N-type transistor with lower current-driving capability turns on at fist, thereby the potential of the memory cell source wire is slowly reduced, and the other transistor with higher current-driving capability turns on afterward. After the memory cell source wire is connected with the ground plane and its potential is perfectly stabilized, the datum stored in the memory cell can be normally read.

    Abstract translation: 本发明的目的是提供一种电可擦除和可编程的非易失性半导体存储器件，其中可以通过抑制存储器单元源极线和一个字的电位的浮动来避免存储在存储单元中的数据的误读 在存储器件的操作从擦除脉冲应用转移到擦除验证的情况下进行连线。 具有不同电流驱动能力的两个晶体管并联连接并插入在存储单元源极线和接地平面之间。 当存储器件的操作从擦除脉冲施加转移到擦除验证时，具有较低电流驱动能力的N型晶体管在第一次导通，从而缓慢地减小存储单元源极线的电位，而另一个具有 较高的电流驱动能力随后开启。 在存储单元源极线与接地平面连接并且其电位完全稳定之后，可以正常读取存储在存储单元中的数据。

    Non-volatile semiconductor memory device having trapped charges pulled out
    17.
    发明授权
    Non-volatile semiconductor memory device having trapped charges pulled out 失效
    被捕获的电荷被拉出的非易失性半导体存储器件

    公开(公告)号：US5930173A

    公开(公告)日：1999-07-27

    申请号：US857038

    申请日：1997-05-15

    Applicant: Mitsuru Sekiguchi

    Inventor： Mitsuru Sekiguchi

    IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

    CPC classification number: G11C16/107 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445

    Abstract: In a method of initializing a flash EEPROM, a pre-programming operation of a predetermined data is first performed in a plurality of memory cells of a memory cell array and then an erasing operation is performed to the plurality of memory cells. Then, a verifying operation of whether the erasing operation is correctly performed is performed. During an initializing operation composed of the pre-programming operation, the erasing operation and the verifying operation, electrons or holes trapped in a tunnel oxide film are pulled out.

    Abstract translation: 在初始化快闪EEPROM的方法中，首先在存储单元阵列的多个存储单元中执行预定数据的预编程操作，然后对多个存储单元执行擦除操作。 然后，执行擦除操作是否正确执行的验证操作。 在由预编程操作，擦除操作和验证操作组成的初始化操作期间，被俘获在隧道氧化膜中的电子或空穴被拉出。

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