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    Method for two-cycle sensing in a two-terminal memory array having leakage current
    11.
    发明申请
    Method for two-cycle sensing in a two-terminal memory array having leakage current 有权

    公开(公告)号：US20080159046A1

    公开(公告)日：2008-07-03

    申请号：US12074448

    申请日：2008-03-03

    Applicant: Darrell Rinerson ,  Christrophe J. Chevallier ,  Chang Hua Siau

    Inventor： Darrell Rinerson ,  Christrophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C5/14

    CPC classification number: G11C11/16 ,  G11C13/004 ,  G11C2013/0057

    Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

    Movable terminal in a two terminal memory array
    15.
    发明申请
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US20060158998A1

    公开(公告)日：2006-07-20

    申请号：US11037971

    申请日：2005-01-18

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  John Sanchez ,  Lawrence Schloss

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  John Sanchez ,  Lawrence Schloss

    IPC: G11B9/00

    CPC classification number: G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    Abstract: A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    Abstract translation: 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

    Cross point array using distinct voltages
    17.
    发明授权
    Cross point array using distinct voltages 有权
    交叉点阵列使用不同的电压

    公开(公告)号：US07020012B2

    公开(公告)日：2006-03-28

    申请号：US11012059

    申请日：2004-12-13

    Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward

    IPC: G11C11/02

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

    Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.

    Abstract translation: 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，两个导电阵列线是唯一限定的。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 非选择电压可以近似等于第一选择电压和第二选择电压的平均值。

    Conductive memory stack with non-uniform width
    18.
    发明授权
    Conductive memory stack with non-uniform width 有权
    具有不均匀宽度的导电存储器堆叠

    公开(公告)号：US07009235B2

    公开(公告)日：2006-03-07

    申请号：US10605963

    申请日：2003-11-10

    Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier

    IPC: H01L27/108

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

    Abstract translation: 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。

    Memory element having islands
    19.
    发明申请
    Memory element having islands 有权
    具有岛的存储元件

    公开(公告)号：US20060028864A1

    公开(公告)日：2006-02-09

    申请号：US11021600

    申请日：2004-12-23

    Applicant: Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

    Inventor： Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

    IPC: G11C11/00

    CPC classification number: G11C11/16

    Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

    Abstract translation: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。

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