公开(公告)号：US20060028864A1

公开(公告)日：2006-02-09

申请号：US11021600

申请日：2004-12-23

Applicant: Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

Inventor： Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

Abstract translation: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。