公开(公告)号：US20230413544A1

公开(公告)日：2023-12-21

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C7/18 ,  H10B43/27 ,  H10B41/10 ,  H10B43/10 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20230389336A1

公开(公告)日：2023-11-30

申请号：US18446586

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B61/00 ,  H01L21/02 ,  H01L29/24 ,  H10N50/01

CPC classification number: H10B61/22 ,  H01L21/02565 ,  H01L29/24 ,  H10N50/01

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US20230386827A1

公开(公告)日：2023-11-30

申请号：US18446953

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/02181 ,  H01L29/66795 ,  H01L21/76829 ,  H01L21/02356 ,  H01L21/02667 ,  H01L29/785 ,  H01L29/42364 ,  H01L21/76871 ,  H01L21/02609 ,  H01L29/66545

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

公开(公告)号：US20230378310A1

公开(公告)日：2023-11-23

申请号：US18362064

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/516 ,  H01L29/42364 ,  H01L21/823857 ,  H01L21/823821 ,  H01L21/28185 ,  H01L29/6684 ,  H01L29/517 ,  H01L29/78391 ,  H01L21/266 ,  H01L29/66545 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/31111 ,  H01L21/31053

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US20230378294A1

公开(公告)日：2023-11-23

申请号：US18366410

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Te-Yang Lai ,  Kuei-Lun Lin ,  Xiong-Fei Yu ,  Chi On Chui ,  Tsung-Da Lin ,  Cheng-Hao Hou

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0924 ,  H01L2029/7858

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

公开(公告)号：US20230378179A1

公开(公告)日：2023-11-23

申请号：US17815078

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/8258 ,  H01L29/66969

Abstract: A method includes forming a thin-film omega transistor, which includes forming a gate fin over a dielectric layer, forming a gate dielectric on sidewalls and a top surface of the gate fin, and depositing an oxide semiconductor layer over the gate dielectric. The gate fin, the gate dielectric, and the oxide semiconductor layer collectively form a fin structure. A source region is formed to contact first sidewalls and a first top surface of a first portion of the oxide semiconductor layer. A drain region is formed to contact second sidewalls and a second top surface of a second portion of the oxide semiconductor layer.

公开(公告)号：US20230369472A1

公开(公告)日：2023-11-16

申请号：US18358377

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L21/0228 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

公开(公告)号：US11817489B2

公开(公告)日：2023-11-14

申请号：US17521344

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L29/516 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/66545

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US11798809B2

公开(公告)日：2023-10-24

申请号：US17397632

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L21/28185 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376

Abstract: Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

公开(公告)号：US20230335551A1

公开(公告)日：2023-10-19

申请号：US17896970

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Teng Chuang ,  Kuei-Lun Lin ,  Te-Yang Lai ,  Da-Yuan Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the deposition, diffusion, and removal of dipole materials in order to provide different dipole regions within different transistors. These different dipole regions cause the different transistors to have different threshold voltages.