公开(公告)号：US12302636B2

公开(公告)日：2025-05-13

申请号：US17869086

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/12 ,  G11C11/22 ,  H01L21/84 ,  H10B51/20 ,  H10B51/30 ,  H10D30/01 ,  H10D30/69 ,  H10D64/01 ,  H10D64/68 ,  H10D86/00 ,  H10D86/01 ,  H10D87/00

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

公开(公告)号：US12154986B2

公开(公告)日：2024-11-26

申请号：US18447153

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

公开(公告)号：US20240387728A1

公开(公告)日：2024-11-21

申请号：US18787436

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

公开(公告)号：US12136659B2

公开(公告)日：2024-11-05

申请号：US18362064

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US12040387B2

公开(公告)日：2024-07-16

申请号：US18358066

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US11910617B2

公开(公告)日：2024-02-20

申请号：US17098919

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L29/66 ,  H01L29/786 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H10B51/20

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

公开(公告)号：US11903189B2

公开(公告)日：2024-02-13

申请号：US16924903

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Han-Jong Chia ,  Chenchen Jacob Wang ,  Yu-Ming Lin

IPC: H10B41/27 ,  H01L29/06 ,  H01L29/423 ,  H10B41/30 ,  G11C16/24 ,  G11C16/08

CPC classification number: H10B41/27 ,  G11C16/08 ,  G11C16/24 ,  H01L29/0669 ,  H01L29/42392 ,  H10B41/30

Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.

公开(公告)号：US20230413544A1

公开(公告)日：2023-12-21

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C7/18 ,  H10B43/27 ,  H10B41/10 ,  H10B43/10 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20230378310A1

公开(公告)日：2023-11-23

申请号：US18362064

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/516 ,  H01L29/42364 ,  H01L21/823857 ,  H01L21/823821 ,  H01L21/28185 ,  H01L29/6684 ,  H01L29/517 ,  H01L29/78391 ,  H01L21/266 ,  H01L29/66545 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/31111 ,  H01L21/31053

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US20230378179A1

公开(公告)日：2023-11-23

申请号：US17815078

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/8258 ,  H01L29/66969

Abstract: A method includes forming a thin-film omega transistor, which includes forming a gate fin over a dielectric layer, forming a gate dielectric on sidewalls and a top surface of the gate fin, and depositing an oxide semiconductor layer over the gate dielectric. The gate fin, the gate dielectric, and the oxide semiconductor layer collectively form a fin structure. A source region is formed to contact first sidewalls and a first top surface of a first portion of the oxide semiconductor layer. A drain region is formed to contact second sidewalls and a second top surface of a second portion of the oxide semiconductor layer.