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公开(公告)号：US20240128145A1
公开(公告)日：2024-04-18
申请号：US18469111
申请日：2023-09-18
发明人： HYEONSEOK LEE , DONGKYU KIM , HYEONJEONG HWANG
IPC分类号： H01L23/367 , H01L21/306 , H01L21/308 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/373 , H01L23/498 , H01L25/065 , H01L25/10 , H10B80/00
CPC分类号： H01L23/367 , H01L21/30608 , H01L21/3086 , H01L21/4878 , H01L21/561 , H01L21/565 , H01L23/3107 , H01L23/3738 , H01L23/49822 , H01L24/16 , H01L24/95 , H01L25/0655 , H01L25/105 , H10B80/00 , H01L2224/16227 , H01L2224/16238 , H01L2224/95 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/15174 , H01L2924/3511
摘要： A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.
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公开(公告)号：US11955399B2
公开(公告)日：2024-04-09
申请号：US18137803
申请日：2023-04-21
发明人： Ae-Nee Jang , Seung-Duk Baek , Tae-Heon Kim
IPC分类号： H01L23/34 , H01L23/31 , H01L23/367 , H01L23/373 , H01L23/48 , H01L23/498 , H01L23/538
CPC分类号： H01L23/367 , H01L23/3157 , H01L23/3738 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/5384
摘要： A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.
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公开(公告)号：US11942534B2
公开(公告)日：2024-03-26
申请号：US17745178
申请日：2022-05-16
发明人： Hong Yu , Judson R. Holt , Vibhor Jain
IPC分类号： H01L29/737 , H01L23/373 , H01L29/66
CPC分类号： H01L29/737 , H01L23/3738 , H01L29/66242
摘要： The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.
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公开(公告)号：US11929311B2
公开(公告)日：2024-03-12
申请号：US17502706
申请日：2021-10-15
发明人： Vivek K Arora , Woochan Kim
IPC分类号： H01L23/495 , H01F27/28 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/373
CPC分类号： H01L23/49575 , H01F27/2804 , H01L21/56 , H01L23/3107 , H01L23/3738 , H01L23/49513 , H01L23/49562 , H01L24/48 , H01L24/73 , H01L24/92 , H01F2027/2809 , H01L2224/48175 , H01L2224/48195 , H01L2224/73265 , H01L2224/92247
摘要： A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.
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公开(公告)号：US11881441B2
公开(公告)日：2024-01-23
申请号：US16642815
申请日：2017-09-29
申请人： Intel Corporation
发明人： Sireesha Gogineni , Andrew Kim , Yong She , Karissa J. Blue
IPC分类号： H01L23/373 , H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
CPC分类号： H01L23/3738 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/73265 , H01L2225/0651 , H01L2225/06506 , H01L2225/06568
摘要： Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.
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公开(公告)号：US11876032B2
公开(公告)日：2024-01-16
申请号：US17504316
申请日：2021-10-18
IPC分类号： H01L23/373 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00 , H01L29/737
CPC分类号： H01L23/3738 , H01L23/3736 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L24/05 , H01L24/24 , H01L29/7371 , H01L2224/05644 , H01L2224/08145 , H01L2224/1357 , H01L2224/13147 , H01L2224/13644 , H01L2224/24146
摘要： A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.
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127.发明公开公开(公告)号：US20230395456A1
公开(公告)日：2023-12-07
申请号：US17831100
申请日：2022-06-02
申请人： Intel Corporation
IPC分类号： H01L23/367 , H01L23/528 , H01L23/373
CPC分类号： H01L23/3672 , H01L23/3738 , H01L23/5283
摘要： Thermally conductive, electrically insulating materials and their manufacture on integrated circuit (IC) dies. An IC die may include a substrate with transistors on one side and, on the first and/or a second side, electrically insulating materials enhanced with thermally conductive materials. Such an IC die may be included in a system with a power supply. Such materials may be co-deposited, or interspersed, or interleaved together in a composite material.
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公开(公告)号：US11769707B2
公开(公告)日：2023-09-26
申请号：US17576705
申请日：2022-01-14
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Fei Zhou
IPC分类号： H01L23/373 , H01L29/66 , H01L29/78 , H01L21/76 , H01L21/02 , H01L29/06 , H01L23/367
CPC分类号： H01L23/3738 , H01L21/02252 , H01L21/76 , H01L23/367 , H01L29/0649 , H01L29/6681 , H01L29/66818 , H01L29/7851
摘要： A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region.
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公开(公告)号：US20230290868A1
公开(公告)日：2023-09-14
申请号：US17745178
申请日：2022-05-16
发明人： Hong Yu , Judson R. Holt , Vibhor Jain
IPC分类号： H01L29/737 , H01L29/66 , H01L23/373
CPC分类号： H01L29/737 , H01L29/66242 , H01L23/3738
摘要： The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.
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公开(公告)号：US20230290705A1
公开(公告)日：2023-09-14
申请号：US17693668
申请日：2022-03-14
发明人： Cheng-Chin LEE , Shau-Lin SHUE , Shao-Kuan LEE , Hsiao-Kang CHANG , Cherng-Shiaw TSAI , Kai-Fang CHENG , Hsin-Yen HUANG , Ming-Hsien LIN , Chuan-Pu CHOU , Hsin-Ping CHEN , Chia-Tien WU , Kuang-Wei YANG
IPC分类号： H01L23/373 , H01L29/78 , H01L27/088 , H01L23/522 , H01L23/528
CPC分类号： H01L23/3738 , H01L29/7851 , H01L27/0886 , H01L23/3732 , H01L23/5226 , H01L23/5283
摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.
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