公开(公告)号：US11664292B2

公开(公告)日：2023-05-30

申请号：US17340197

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

公开(公告)号：US11955399B2

公开(公告)日：2024-04-09

申请号：US18137803

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

公开(公告)号：US09530670B2

公开(公告)日：2016-12-27

申请号：US14492122

申请日：2014-09-22

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Hoon Han ,  Byoung-Moon Yoon ,  Young-Taek Hong ,  Keon-Young Kim ,  Jun-Youl Yang ,  Young-Ok Kim ,  Tae-Heon Kim ,  Sun-Joong Song ,  Jung-Hun Lim ,  Jae-Wan Park ,  Jin-Uk Lee

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/3213 ,  H01L29/423 ,  C09K13/04 ,  C23F1/26 ,  H01L21/321 ,  H01L27/115 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/32133 ,  C09K13/04 ,  C23F1/26 ,  H01L21/32115 ,  H01L21/32134 ,  H01L27/11582 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Abstract translation: 本公开内容涉及形成导电图案的方法以及使用其形成半导体器件的方法。 在一些实施例中，形成导电图案的方法包括在衬底上形成第一导电层和第二导电层。 第一导电层和第二导电层可以分别包括金属氮化物和金属。 可以使用包括磷酸，硝酸，辅助氧化剂和剩余的水的蚀刻剂组合物来蚀刻第一导电层和第二导电层。 蚀刻剂组合物可以具有与金属氮化物和金属基本相同的蚀刻速率。

公开(公告)号：US11056414B2

公开(公告)日：2021-07-06

申请号：US16507974

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

公开(公告)号：US20150200112A1

公开(公告)日：2015-07-16

申请号：US14492122

申请日：2014-09-22

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Hoon Han ,  Byoung-Moon Yoon ,  Young-Taek Hong ,  Keon-Young Kim ,  Jun-Youl Yang ,  Young-Ok Kim ,  Tae-Heon Kim ,  Sun-Joong Song ,  Jung-Hun Lim ,  Jae-Wan Park ,  Jin-Uk Lee

IPC: H01L21/3213 ,  H01L29/423 ,  C23F1/16 ,  H01L21/02

CPC classification number: H01L21/32133 ,  C09K13/04 ,  C23F1/26 ,  H01L21/32115 ,  H01L21/32134 ,  H01L27/11582 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Abstract translation: 本公开内容涉及形成导电图案的方法以及使用其形成半导体器件的方法。 在一些实施例中，形成导电图案的方法包括在衬底上形成第一导电层和第二导电层。 第一导电层和第二导电层可以分别包括金属氮化物和金属。 可以使用包括磷酸，硝酸，辅助氧化剂和剩余的水的蚀刻剂组合物来蚀刻第一导电层和第二导电层。 蚀刻剂组合物可以具有与金属氮化物和金属基本相同的蚀刻速率。