公开(公告)号：US20090200669A1

公开(公告)日：2009-08-13

申请号：US12355896

申请日：2009-01-19

Applicant: CHIH-CHAO YANG ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： CHIH-CHAO YANG ,  Mukta Ghate Farooq ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.

Abstract translation: 本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。 互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。 阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

公开(公告)号：US20090090986A1

公开(公告)日：2009-04-09

申请号：US12334746

申请日：2008-12-15

Applicant: Wai-Kin Li ,  Haining Yang

Inventor： Wai-Kin Li ,  Haining Yang

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract translation: 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US20080251878A1

公开(公告)日：2008-10-16

申请号：US11876030

申请日：2007-10-22

Applicant: Jack Allan Mandelman ,  Haining Yang

Inventor： Jack Allan Mandelman ,  Haining Yang

IPC: H01L29/00

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11

Abstract: Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.

Abstract translation: 体现在用于设计，制造或测试其中设计结构包括静态随机存取存储器（SRAM）设备的设计的机器可读介质中的设备结构。 该设计结构包括设置在第一和第二半导体区域之间的介质区域和在第一和第二半导体区域之间延伸的栅极导体结构。 栅极导体结构具有覆盖第一半导体区域的第一侧壁。 该设计结构还包括延伸跨越第一半导体区域的电连接桥。 电连接桥的一部分将第一半导体区域中的杂质掺杂区域与栅极导体结构的第一侧壁电连接。

公开(公告)号：US20080179706A1

公开(公告)日：2008-07-31

申请号：US11627384

申请日：2007-01-26

Applicant: Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

Inventor： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.

Abstract translation: 公开了一种电子可编程保险丝（e-fuse）。 在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

公开(公告)号：US07390745B2

公开(公告)日：2008-06-24

申请号：US11162800

申请日：2005-09-23

Applicant: Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

Inventor： Thomas W. Dyer ,  Kenneth T. Settlemyer, Jr. ,  James J. Toomey ,  Haining Yang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/30608 ,  H01L21/32134

Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.

Abstract translation: 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

公开(公告)号：US07385258B2

公开(公告)日：2008-06-10

申请号：US11380097

申请日：2006-04-25

Applicant: Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

IPC: H01L29/76

CPC classification number: H01L29/7834 ,  H01L21/76816 ,  H01L21/84 ,  H01L23/485 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636

Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.

Abstract translation: 半导体结构及其形成方法。 半导体结构包括（a）半导体层，（b）栅极电介质区域和（c）栅电极区域。 栅电极区域与半导体层电绝缘。 半导体层包括沟道区，第一和第二源极/漏极区。 沟道区域设置在第一和第二源极/漏极区域之间，并且直接位于栅电极区域下方并与栅电极区域电绝缘。 半导体结构还包括（d）第一和第二导电区域，以及（e）第一和第二接触区域。 第一导电区域和第一源极/漏极区域在第一和第二共同表面处彼此直接物理接触。 第一和第二公共表面不共面。 第一接触区域与第一和第二公共表面重叠。

公开(公告)号：US20080122109A1

公开(公告)日：2008-05-29

申请号：US11458464

申请日：2006-07-19

Applicant: Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

Abstract translation: 一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。 该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。 半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

公开(公告)号：US20080122045A1

公开(公告)日：2008-05-29

申请号：US11564314

申请日：2006-11-29

Applicant: Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

Inventor： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

公开(公告)号：US20080093743A1

公开(公告)日：2008-04-24

申请号：US11550966

申请日：2006-10-19

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5329 ,  B81C1/00095 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract translation: 提供了一种形成互连结构的方法，包括纳米尺度，例如亚光刻，线和通孔，用于使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物的半导体技术的未来生成 。 本发明的方法提供了一种互连结构，其中线路与通孔自对准。

公开(公告)号：US20080085585A1

公开(公告)日：2008-04-10

申请号：US11538850

申请日：2006-10-05

Applicant: Haining Yang ,  Xiangdong Chen

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L21/336

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L27/092

Abstract: The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and second gate electrode region comprised of gate material doped with second ions for a second device. The respectively doped regions are connected by a silicide layer near the top surface of the gate conductors.

Abstract translation: 本发明涉及减少掺杂剂交叉扩散并改善芯片密度的改进的晶体管。 本发明的第一实施例包括在由掺杂有用于第一器件的第一离子的栅极材料构成的第一栅极电极区域和由掺杂有第二离子的栅极材料构成的第二栅极电极区域的第一栅极电极区域处部分去除的栅电极材料，用于第二器件 。 分别掺杂的区域通过靠近栅极导体的顶表面的硅化物层连接。