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    Functional command for semiconductor memory
    111.
    发明授权
    Functional command for semiconductor memory 失效
    半导体存储器功能指令

    公开(公告)号：US4507761A

    公开(公告)日：1985-03-26

    申请号：US370172

    申请日：1982-04-20

    申请人： Andrew C. Graham

    发明人： Andrew C. Graham

    IPC分类号： G01R31/317 ,  G06F11/22 ,  G11C7/22 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24 ,  G11C29/44 ,  G11C29/46 ,  G11C7/00

    CPC分类号： G11C29/835 ,  G01R31/31701 ,  G11C29/24 ,  G11C29/44 ,  G11C29/46 ,  G11C29/846 ,  G11C7/22

    摘要： A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array. After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column. With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns. This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array.

    摘要翻译： 描述了用于启动用于半导体存储器电路的所选功能模式的方法和装置。 用于启动所选择的功能模式的方法包括将至少第一操作信号的活动状态施加到存储器电路，然后将第二操作信号的有效状态施加到存储器电路。 相对于第一操作信号的第二操作信号的定时不在用于传送到存储器和从存储器的常规数据传输的第一和第二操作信号的规定的限定范围内。 所选择的功能模式的示例是激活电路（62），其用于将预定数据状态应用于冗余列（63），冗余列（63）可替代以代替存储器阵列内的有缺陷的主列。 在存储器阵列先前已经接收到第一数据状态并且电路（62）被激活以将第二数据状态应用于冗余列（63）之后，存储器阵列被读取，并且产生第二数据状态的每一列被确定为 冗余列。 利用列替换算法的知识，可以确定哪些冗余列已被编程以替换特定的原始列。 因此，尽管将冗余元件并入主存储器阵列中，但是该方法可以确定存储器电路的物理配置。

    Method of and means for in-line testing of a memory operating in time-division mode
    112.
    发明授权
    Method of and means for in-line testing of a memory operating in time-division mode 失效
    以时分模式运行的存储器进行在线测试的方法和装置

    公开(公告)号：US4049956A

    公开(公告)日：1977-09-20

    申请号：US730723

    申请日：1976-10-08

    申请人： Wouter Martinus Dirk Van Veen

    发明人： Wouter Martinus Dirk Van Veen

    IPC分类号： G11C29/02 ,  G11C29/14 ,  G11C29/32 ,  G11C29/36 ,  G11C29/00 ,  G06F11/10

    CPC分类号： G11C29/02 ,  G11C29/14 ,  G11C29/32 ,  G11C29/36

    摘要： A read/write memory of n stages, periodically addressed in a recurrent scanning cycle of n time slots in which binary words are written in and read out from respective stages, is connected to a data-handling network by way of a writing multiple and a reading multiple each traversing a respective selective inverter, i.e., an upstream inverter in the writing multiple and a downstream inverter in the reading multiple. The two inverters are controlled by a generator of pseudo-random binary signals, unrelated to those processed in the data-handling network, having an operating cycle coextensive with a scanning cycle. Depending on the character of the control signals issuing from this pseudo-random generator during each cycle, the two selective inverters pass the bits of their incoming words either in their original or in a complemented form; with words written in a memory stage in one cycle read out in the immediately following cycle, the control signals delivered to the two inverters are identical but staggered by one cycle so that the words appearing in the output of the downstream inverter match those fed into the upstream inverter in the preceding cycle when the memory operates properly. Under certain circumstances, when a memory stage is addressed out of turn so that loading and reading of its contents occur successively in the same cycle, the staggering of the two control signals is canceled. Malfunctions of the memory are detected by parity checks carried out on the words traveling along the reading multiple to the downstream inverter; an alarm signal is emitted upon the occurrence of an error in the same bit position in two consecutive cycles.

    摘要翻译： 在其中二进制字被写入并从各个级读出的n个时隙的周期性地寻址的n个级的读/写存储器通过写入多个和一个数据处理网络连接到数据处理网络 读取多个，遍历相应的选择性逆变器，即写入倍数中的上游逆变器和读取倍数中的下游逆变器。 两个逆变器由与数据处理网络中处理的那些无关的伪随机二进制信号的发生器控制，具有与扫描周期共同延伸的操作周期。 根据在每个周期期间从该伪随机发生器发出的控制信号的特性，两个选择性反相器以它们的原始或补码的形式传递它们的输入字的位; 在紧随其后的周期中，在一个周期中写入存储器级的字读出，传送到两个反相器的控制信号相同但交错一个周期，使得出现在下游逆变器的输出中的字与馈送到 上游逆变器在上一个周期中，当存储器运行正常时。 在某些情况下，当记忆级被转向寻址时，其内容的加载和读取在同一周期内连续出现，两个控制信号的交错被取消。 通过对沿着读取倍数行进的字对下游逆变器执行的奇偶校验来检测存储器的故障; 在两个连续的周期内发生相同比特位置的错误时发出报警信号。

    Techniques for detecting a state of a bus
    114.
    发明授权
    Techniques for detecting a state of a bus 有权

    公开(公告)号：US12046316B2

    公开(公告)日：2024-07-23

    申请号：US17502982

    申请日：2021-10-15

    申请人： Micron Technology, Inc.

    发明人： Scott E. Schaefer ,  Aaron P. Boehm

    IPC分类号： G11C8/18 ,  G11C29/12 ,  G11C29/14 ,  G11C29/42

    CPC分类号： G11C29/42 ,  G11C8/18 ,  G11C29/12005 ,  G11C29/14 ,  G11C2029/1208

    摘要： Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

    Memory, memory test system, and memory test method
    117.
    发明授权
    Memory, memory test system, and memory test method 有权

    公开(公告)号：US11817166B2

    公开(公告)日：2023-11-14

    申请号：US17650317

    申请日：2022-02-08

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Jia Wang

    IPC分类号： G11C29/12 ,  G11C29/14 ,  G11C29/36

    CPC分类号： G11C29/12015 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/3602

    摘要： A memory includes: an input circuit, configured to: receive an outside clock signal, and output a first test clock signal; a test path selection circuit, connected to the input circuit, and configured to output a second test clock signal according to a read clock command; and an output circuit, connected to the test path selection circuit, and configured to convert the second test clock signal into a third test clock signal and output the third test clock signal to outside of the memory. In the embodiments of the disclosure, a time delay of inputting a clock signal into each chip under test is quantified, to acquire an actual output delay of the chip, thereby improving the accuracy of parallel tests of a plurality of chips.

    Quick configurable universal register for a configurable integrated circuit die
    118.
    发明授权
    Quick configurable universal register for a configurable integrated circuit die 有权

    公开(公告)号：US11749368B2

    公开(公告)日：2023-09-05

    申请号：US16729085

    申请日：2019-12-27

    申请人： Intel Corporation

    发明人： Bee Yee Ng ,  Dana How

    IPC分类号： G11C29/12 ,  G11C29/56 ,  G11C29/00 ,  G11C29/14 ,  G06F15/78

    CPC分类号： G11C29/12015 ,  G06F15/7807 ,  G11C29/14 ,  G11C29/56008 ,  G11C29/789 ,  G11C2029/1206

    摘要： An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.