公开(公告)号：US09793171B2

公开(公告)日：2017-10-17

申请号：US15179620

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L21/285

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

公开(公告)号：US20170288040A1

公开(公告)日：2017-10-05

申请号：US15088960

申请日：2016-04-01

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Emmanuel Augendre ,  Qing Liu ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/225 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/2257 ,  H01L21/3065 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins being formed of Si or SiGe; depositing a silicon oxide layer over the SiGe layer; and forming an SiGe channel formation region within each fin by performing Ge enrichment to diffuse Ge atoms from the SiGe layer into the one or more fins.

公开(公告)号：US09748351B2

公开(公告)日：2017-08-29

申请号：US15273777

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

公开(公告)号：US20170200807A1

公开(公告)日：2017-07-13

申请号：US15471733

申请日：2017-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US20170110583A1

公开(公告)日：2017-04-20

申请号：US15396743

申请日：2017-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US09601511B2

公开(公告)日：2017-03-21

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud Vinet ,  Kangguo Cheng ,  Bruce Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/223 ,  H01L21/265 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

公开(公告)号：US20170033221A1

公开(公告)日：2017-02-02

申请号：US14812425

申请日：2015-07-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract translation: 半导体器件包括在衬底中图案化的鳍; 设置在所述翅片上并基本上垂直于所述翅片的门; 一对外延触点，包括在鳍的上方和栅极的相对侧上的III-V材料; 以及在栅极下方的一对外延触点之间的沟道区，包括在掺杂III-V材料之间的未掺杂的III-V材料，掺杂的III-V材料包括量为约1e18至约1e20原子/ 并与外延触点接触。

公开(公告)号：US09559018B2

公开(公告)日：2017-01-31

申请号：US15252315

申请日：2016-08-31

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

公开(公告)号：US20160372493A1

公开(公告)日：2016-12-22

申请号：US15252315

申请日：2016-08-31

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

公开(公告)号：US09515185B2

公开(公告)日：2016-12-06

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Hong He ,  Bruce Doris

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 结构稳定的绝缘体上的FinFET采用氮化硅衬垫以防止SiGe鳍底部的稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。