公开(公告)号：US07256084B2

公开(公告)日：2007-08-14

申请号：US11122667

申请日：2005-05-04

Applicant: Khee Yong Lim ,  Wenhe Lin ,  Chung Woh Lai ,  Yong Meng Lee ,  Liang Choo Hsia ,  Young Way Teh ,  John Sudijono ,  Wee Leng Tan ,  Hui Peng Koh

Inventor： Khee Yong Lim ,  Wenhe Lin ,  Chung Woh Lai ,  Yong Meng Lee ,  Liang Choo Hsia ,  Young Way Teh ,  John Sudijono ,  Wee Leng Tan ,  Hui Peng Koh

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

Abstract translation: 示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。 我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。 我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。 中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。 这提高了设备​​性能。

公开(公告)号：US07253097B2

公开(公告)日：2007-08-07

申请号：US11160624

申请日：2005-06-30

Applicant: Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

Inventor： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

Abstract translation: 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

公开(公告)号：US20070090484A1

公开(公告)日：2007-04-26

申请号：US11162027

申请日：2005-08-25

Applicant: Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

Inventor： Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

IPC: H01L29/00

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

Abstract: An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.

Abstract translation: 提供集成电路应力控制系统。 栅极形成在衬底上，并且沟道形成在衬底中。 源极/漏极围绕栅极形成。 在衬底中形成浅沟槽隔离，通道上的浅沟槽隔离产生应变。 在基板上形成应力抑制特征。

公开(公告)号：US20070001303A1

公开(公告)日：2007-01-04

申请号：US11160624

申请日：2005-06-30

Applicant: Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

Inventor： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

IPC: H01L23/52

CPC classification number: H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

Abstract translation: 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

公开(公告)号：US07153766B2

公开(公告)日：2006-12-26

申请号：US10339188

申请日：2003-01-09

Applicant: Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

Inventor： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

公开(公告)号：US20060252188A1

公开(公告)日：2006-11-09

申请号：US10908328

申请日：2005-05-06

Applicant: Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

Inventor： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

Abstract translation: 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US07094669B2

公开(公告)日：2006-08-22

申请号：US10910499

申请日：2004-08-03

Applicant: Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

Inventor： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/76 ,  H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

公开(公告)号：US07084025B2

公开(公告)日：2006-08-01

申请号：US10885855

申请日：2004-07-07

Applicant: Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

Inventor： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/305 ,  H01L21/4763

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

Abstract: A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

Abstract translation: 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 PLDD区域之间的间隔优选比由于较宽的PMOS间隔物而在NLDD区域之间的间隔更大。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

公开(公告)号：US20060099518A1

公开(公告)日：2006-05-11

申请号：US10985263

申请日：2004-11-10

Applicant: Sia Tan ,  Qunying Lin ,  Liang-Choo Hsia

Inventor： Sia Tan ,  Qunying Lin ,  Liang-Choo Hsia

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/30

Abstract: A embodiment method for forming a layout for a phase shift mask. A embodiment comprises providing a layout comprising a first feature, a first shifter region and a second shifter region. The first feature preferably has a L-shape portion with an elbow region. The first shifter region is on the outside of the L-shaped portion and the second shifter region is on the inside of the L-shaped portion. The elbow region has an outside corner away from the second shifter region. We identify a phase conflict region caused by the L-shaped portion of the first feature, the first shifter region and the second shifter region. We resolve the phase conflict by modifying the elbow region by moving the outside corner of the elbow region away from the first shifter region and the phase conflict region. The modification of the elbow region further comprises forming a jog region in the line end section of the first feature.

Abstract translation: 一种用于形成相移掩模布局的实施例方法。 实施例包括提供包括第一特征，第一移位区和第二移位区的布局。 第一特征优选具有肘部区域的L形部分。 第一移位区域位于L形部分的外侧，第二移位区域位于L形部分的内侧。 肘部区域具有远离第二移位区域的外角。 我们识别由第一特征的L形部分，第一移位区域和第二移位区域引起的相位冲突区域。 我们通过移动肘部区域的外角远离第一移位区域和相位冲突区域来修改肘部区域来解决相位冲突。 肘部区域的修改还包括在第一特征的线端部中形成点动区域。

公开(公告)号：US20060088995A1

公开(公告)日：2006-04-27

申请号：US11299457

申请日：2005-12-12

Applicant: Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

Inventor： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

Abstract translation: 提供了一种用于创建铜互连的新方法。 产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。 保护层被图案化和蚀刻，暴露铜互连图案的表面。 暴露的铜表面是Ar溅射，之后沉积第一势垒层。 去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。 沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。 通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。 沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。