公开(公告)号：US07528445B2

公开(公告)日：2009-05-05

申请号：US11380378

申请日：2006-04-26

Applicant: Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

Inventor： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC: H01L29/76 ,  H01L31/113 ,  H01L21/338

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

Abstract translation: 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US20060180848A1

公开(公告)日：2006-08-17

申请号：US11380378

申请日：2006-04-26

Applicant: Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

Inventor： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

Abstract translation: 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US06410429B1

公开(公告)日：2002-06-25

申请号：US09795113

申请日：2001-03-01

Applicant: Chaw Sing Ho ,  Kheng Chok Tee ,  Kin Leong Pey ,  G. Karunasiri ,  Soo Jin Chua ,  Kong Hean Lee ,  Alex Kalhung See

Inventor： Chaw Sing Ho ,  Kheng Chok Tee ,  Kin Leong Pey ,  G. Karunasiri ,  Soo Jin Chua ,  Kong Hean Lee ,  Alex Kalhung See

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/28518 ,  H01L29/665

Abstract: A method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550° C. and 580° C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi2/CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825° C. and 875° C. to convert the CoSi2/CoSi layer to a CoSi2 layer. The CoSi2 layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.

Abstract translation: 在超浅源极/漏极结上形成无空隙的外延钴硅化物（CoSi 2）层的方法。 使用HF清洁图案化的硅结构。 在图案化的硅衬底上依次形成第一钛层，钴层和第二钛层。 图案化的硅衬底在大气压下在氮气环境中在约550℃和580℃之间的温度下退火; 由此钴向下迁移并与硅结构反应以形成CoSi 2 / CoSi层，并且第一钛层向上迁移，并且第一钛层和第二钛层与硝化环境反应形成TiN。 去除TiN和未反应的钴。 将硅结构在约825℃和875℃之间的温度下退火，以将CoSi 2 / CoSi层转化为CoSi 2层。 CoSi2层可以任选地被杂质离子注入，后者被扩散以形成超浅结。

公开(公告)号：US07084025B2

公开(公告)日：2006-08-01

申请号：US10885855

申请日：2004-07-07

Applicant: Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

Inventor： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/305 ,  H01L21/4763

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

Abstract: A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

Abstract translation: 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 PLDD区域之间的间隔优选比由于较宽的PMOS间隔物而在NLDD区域之间的间隔更大。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

公开(公告)号：US06998682B2

公开(公告)日：2006-02-14

申请号：US11128010

申请日：2005-05-12

Applicant: Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

Inventor： Yeen Tat Chan ,  Kheng Chok Tee ,  Yiang Aun Nga ,  Zhao Lun ,  Wang Ling Goh ,  Diing Shenp Ang

IPC: H01L27/01

CPC classification number: H01L29/66772 ,  H01L29/78615

Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Abstract translation: 已经开发了在绝缘体上硅层上形成的MOSFET器件结构以及用于制造所述MOSFET器件结构的工艺顺序。 该工艺具有在MOSFET器件结构的特定位置形成的绝缘体填充的浅沟槽隔离（STI）区域，用于降低栅极结构结下方的寄生晶体管形成的风险。 在形成“T”形或“H”形栅极结构之后，形成与STI区域和栅极结构的部件相邻的第一导电类型的主体接触区域。 接下来进行位于相同STI区域的相反侧的第二导电类型的源极/漏极区域的形成以及相同的栅极结构部件。 通过存在分离的STI区域可以防止通过体接触区域和源极/漏极区域发生在栅极结构下方的不需要的寄生晶体管形成。

公开(公告)号：US06468906B1

公开(公告)日：2002-10-22

申请号：US09617009

申请日：2000-07-14

Applicant: Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

Inventor： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

IPC: H01L2144

CPC classification number: H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886

Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

Abstract translation: 在IMD层中的互连孔中形成半导体器件上的IMD层上的互连线。 互连孔在IMD层中具有壁和底部。 在孔的壁和底部形成扩散阻挡层。 用铜金属线填充互连孔。 执行CMP步骤以使器件平坦化，并移除IMD层上方的铜。 在孔的顶部包埋铜金属线的铜金属线的表面上沉积钝化金属层。 或者，铜金属线层的覆盖沉积覆盖扩散层并用铜金属线填充互连孔。 执行CMP工艺以平坦化器件以去除IMD层上方的铜。 在自对准沉积工艺中，在孔的顶部封装铜金属线的铜金属线的表面上沉积钝化金属层。

公开(公告)号：US06319772B1

公开(公告)日：2001-11-20

申请号：US09697946

申请日：2000-10-30

Applicant: Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

Inventor： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

IPC: H01L218242

CPC classification number: H01L27/10873 ,  H01L27/10808

Abstract: Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

Abstract translation: 使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。 选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

公开(公告)号：US06268276B1

公开(公告)日：2001-07-31

申请号：US09216823

申请日：1998-12-21

Applicant: Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

Inventor： Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

IPC: H01L214763

CPC classification number: H01L21/7682

Abstract: A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.

Abstract translation: 在半导体电路的相邻导线之间通过使用“各处的孔”形成气隙的新方法或可用于在电介质层中产生孔的“反向金属孔”掩模。 被蚀刻的电介质已经沉积在导电线之间，以这种方式形成的孔通过在孔的顶部沉积电介质来封闭。 可以在沉积的电介质的整个层上蚀刻孔，或者可以在导电线之间蚀刻孔。

公开(公告)号：US07202133B2

公开(公告)日：2007-04-10

申请号：US10761613

申请日：2004-01-21

Applicant: King Jien Chui ,  Francis Benistant ,  Ganesh Shamkar Samudra ,  Kian Meng Tee ,  Yisuo Li ,  Kum Woh Vincent Leong ,  Kheng Chok Tee

Inventor： King Jien Chui ,  Francis Benistant ,  Ganesh Shamkar Samudra ,  Kian Meng Tee ,  Yisuo Li ,  Kum Woh Vincent Leong ,  Kheng Chok Tee

IPC: H01L21/26

CPC classification number: H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

公开(公告)号：US07169675B2

公开(公告)日：2007-01-30

申请号：US10886442

申请日：2004-07-07

Applicant: Chung Foong Tan ,  Jinping Liu ,  Hyeokjae Lee ,  Kheng Chok Tee ,  Elgin Quek

Inventor： Chung Foong Tan ,  Jinping Liu ,  Hyeokjae Lee ,  Kheng Chok Tee ,  Elgin Quek

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/1083

Abstract: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.

Abstract translation: 在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。 含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。 示例性实施例示出了在FET下面的含C层。 其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。 可以使用低温退火，因为含碳层减少了缺陷。