公开(公告)号：US09396939B2

公开(公告)日：2016-07-19

申请号：US14678119

申请日：2015-04-03

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato

IPC分类号： H01L21/322 ,  H01L21/02 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L21/02554 ,  H01L21/02488 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

公开(公告)号：US09390942B2

公开(公告)日：2016-07-12

申请号：US13831067

申请日：2013-03-14

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Hiroshi Domyo ,  Michael McCafferty ,  Alain Duvallet ,  Masaki Sato ,  Christopher O'Brien ,  Anthony Mark Miscione ,  George Imthurn

IPC分类号： H01L21/332 ,  H01L21/322 ,  H01L21/02 ,  H01L29/36 ,  H01L23/31 ,  H01L21/762 ,  H01L23/26

CPC分类号： H01L21/3226 ,  H01L21/02052 ,  H01L21/3221 ,  H01L21/76251 ,  H01L21/76256 ,  H01L23/26 ,  H01L23/3128 ,  H01L29/36 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

摘要翻译： 本文描述了制备用于随后与半导体层接合的衬底的实施例。 可以用一种或多种化学品或牺牲层制备基底以限制或去除基底污染物并减少基底表面损伤。 可以描述和要求保护其他实施例。

公开(公告)号：US09373516B2

公开(公告)日：2016-06-21

申请号：US14016027

申请日：2013-08-30

申请人： Khaled Z. Ahmed ,  Steven Hung ,  Kaushal K. Singh ,  Sundar Ramamurthy

发明人： Khaled Z. Ahmed ,  Steven Hung ,  Kaushal K. Singh ,  Sundar Ramamurthy

IPC分类号： H01L21/322 ,  H01L21/30 ,  H01L21/67 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

CPC分类号： H01L21/3003 ,  H01L21/02164 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/6715 ,  H01L21/67207 ,  H01L29/66545

摘要： Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing.

摘要翻译： 提供了用于将用作栅极堆叠中的沟道的衬底表面功能化的方法和装置。 硅，锗和锗锗衬底表面通过等离子体处理中的一种或多种硫和硒进行功能化。

公开(公告)号：US09343542B2

公开(公告)日：2016-05-17

申请号：US14550521

申请日：2014-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Alexander Kalnitsky ,  Chih-Wen Hsiung ,  Chun Lin Tsai

IPC分类号： H01L21/338 ,  H01L21/322 ,  H01L29/66 ,  H01L29/205 ,  H01L29/207 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/66143 ,  H01L29/7787

摘要： A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second III-V compound layer on the first III-V compound layer. The second III-V compound layer is different from the first III-V compound layer. A gate stack is formed thereon. The forming of the gate stack further includes forming a diode having a pair of a n-type doped III-V compound layer and a p-type doped III-V compound layer. Source and drain features are formed on the second III-V compound layer and interposed by the gate stack.

摘要翻译： 描述制造增强型晶体管的方法。 该方法包括在衬底上形成第一III-V化合物层，并在第一III-V化合物层上形成第二III-V化合物层。 第二III-V化合物层与第一III-V族化合物层不同。 在其上形成栅极堆叠。 栅堆叠的形成还包括形成具有一对n型掺杂III-V化合物层和p型掺杂III-V化合物层的二极管。 源极和漏极特征形成在第二III-V复合层上并由栅极叠层插入。

公开(公告)号：US09337194B2

公开(公告)日：2016-05-10

申请号：US14617409

申请日：2015-02-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/322 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08 ,  H01L21/266 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L27/092 ,  H01L21/266 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.

公开(公告)号：US20160118267A1

公开(公告)日：2016-04-28

申请号：US14989249

申请日：2016-01-06

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人： Takeshi Araya ,  Tsutomu Komatani

IPC分类号： H01L21/322 ,  H01L29/20 ,  H01L21/324 ,  H01L29/66

CPC分类号： H01L21/3228 ,  H01L21/3221 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7787

摘要： A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

摘要翻译： 一种制造半导体器件的方法，包括：在包括FET的沟道层的氮化物半导体层的上表面上形成硅层; 在形成硅层的过程中或在形成硅层的工艺之后对氮化物半导体层进行热处理; 以及在形成所述硅层的工艺之后，在所述硅层的上表面上形成绝缘层。

公开(公告)号：US09318338B2

公开(公告)日：2016-04-19

申请号：US13969616

申请日：2013-08-19

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Bor-Shyang Liao ,  Tsung-Hsun Tsai ,  Kuo-Chih Lai ,  Pin-Hong Chen ,  Chia-Chang Hsu ,  Shu-Min Huang ,  Min-Chung Cheng ,  Chun-Ling Lin

IPC分类号： H01L21/322 ,  H01L21/283 ,  H01L21/28 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/285

CPC分类号： H01L21/283 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7833 ,  H01L29/7834

摘要： A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括以下步骤。 首先，提供具有氮化物层和含铂（Pt）的镍（Ni） - 半导体化合物层的衬底。 然后用包含硫酸组分和磷酸组分的化学溶液原位除去氮化物层和Pt。

公开(公告)号：US09306008B2

公开(公告)日：2016-04-05

申请号：US14207880

申请日：2014-03-13

申请人： Dong-soo Lee ,  Myoung-Jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

发明人： Dong-soo Lee ,  Myoung-Jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

IPC分类号： H01L21/336 ,  H01L29/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/322 ,  H01L29/78 ,  H01L29/24

CPC分类号： H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

摘要： The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

摘要翻译： 本公开内容涉及包括III-V族化合物半导体层和电介质层之间的吸氧层的半导体器件以及制造该半导体器件的方法。 半导体器件可以包括化合物半导体层; 设置在所述化合物半导体层上的电介质层; 以及置于化合物半导体层和电介质层之间的吸氧层。 吸氧层包括具有比化合物半导体层的材料更高的氧亲合力的材料。

公开(公告)号：US09299564B2

公开(公告)日：2016-03-29

申请号：US13897666

申请日：2013-05-20

申请人： Varian Semiconductor Equipment Associates, Inc.

发明人： Andrew M. Waite ,  Stanislav S. Todorov

IPC分类号： H01L21/322 ,  H01L21/223 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L21/2236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66803

摘要： Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.

摘要翻译： 公开了将掺杂剂离子注入到半导体晶片的三维特征中的各种方法。 植入物温度可以变化以确保植入后的三维特征具有被非晶化表面层包围的结晶内核。 晶核提供了一种模板，其中可以再生长其它特征的晶体结构。 在一些实施例中，植入能量和植入物温度可各自被修改以实现具有周围非晶化表面层的期望的晶体内核。

公开(公告)号：US09299556B2

公开(公告)日：2016-03-29

申请号：US13976486

申请日：2010-12-31

申请人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

发明人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L21/02 ,  H01L21/322 ,  H01L21/762

CPC分类号： H01L21/3226 ,  H01L21/76254

摘要： A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

摘要翻译： 通过沟槽工艺制备具有掩埋绝缘层的半导体衬底的方法包括以下步骤：提供器件衬底和支撑衬底; 在所述器件基板的表面上形成绝缘层; 在所述器件基板上进行加热处理，以在所述器件基板的表面上形成剥离区域; 将具有绝缘层的器件基板与支撑基板接合，使得绝缘层夹在器件基板和支撑基板之间; 退火和加强粘合界面，使得接合界面的粘附水平满足以下倒角研磨，减薄和抛光工艺中的要求; 在接合的器件基板上进行倒角研磨，变薄和抛光工艺。