公开(公告)号：US09390942B2

公开(公告)日：2016-07-12

申请号：US13831067

申请日：2013-03-14

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Hiroshi Domyo ,  Michael McCafferty ,  Alain Duvallet ,  Masaki Sato ,  Christopher O'Brien ,  Anthony Mark Miscione ,  George Imthurn

IPC分类号： H01L21/332 ,  H01L21/322 ,  H01L21/02 ,  H01L29/36 ,  H01L23/31 ,  H01L21/762 ,  H01L23/26

CPC分类号： H01L21/3226 ,  H01L21/02052 ,  H01L21/3221 ,  H01L21/76251 ,  H01L21/76256 ,  H01L23/26 ,  H01L23/3128 ,  H01L29/36 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

摘要翻译： 本文描述了制备用于随后与半导体层接合的衬底的实施例。 可以用一种或多种化学品或牺牲层制备基底以限制或去除基底污染物并减少基底表面损伤。 可以描述和要求保护其他实施例。

公开(公告)号：US20140151704A1

公开(公告)日：2014-06-05

申请号：US13831067

申请日：2013-03-14

申请人： Peregrine Semiconductor Corporation

发明人： Hiroshi Domyo ,  Michael McCafferty ,  Alain Duvallet ,  Masaki Sato ,  Christopher O'Brien ,  Anthony Mark Miscione ,  George Imthurn

IPC分类号： H01L21/322 ,  H01L29/36

CPC分类号： H01L21/3226 ,  H01L21/02052 ,  H01L21/3221 ,  H01L21/76251 ,  H01L21/76256 ,  H01L23/26 ,  H01L23/3128 ,  H01L29/36 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

摘要翻译： 本文描述了制备用于随后与半导体层接合的衬底的实施例。 可以用一种或多种化学品或牺牲层制备基底以限制或去除基底污染物并减少基底表面损伤。 可以描述和要求保护其他实施例。

公开(公告)号：US20170084478A1

公开(公告)日：2017-03-23

申请号：US15264821

申请日：2016-09-14

申请人： Soitec ,  Peregrine Semiconductor Corporation

发明人： Bich-Yen Nguyen ,  Christophe Maleville ,  Sinan Goktepeli ,  Anthony Mark Miscione ,  Alain Duvallet

IPC分类号： H01L21/763 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L21/763 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L23/66 ,  H01L27/13 ,  H01L29/04 ,  H01L29/16

摘要： The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from the interface of the polycrystalline silicon layer with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the portion.

公开(公告)号：US09824915B2

公开(公告)日：2017-11-21

申请号：US15264821

申请日：2016-09-14

申请人： Soitec ,  Peregrine Semiconductor Corporation

发明人： Bich-Yen Nguyen ,  Christophe Maleville ,  Sinan Goktepeli ,  Anthony Mark Miscione ,  Alain Duvallet

IPC分类号： H01L21/763 ,  H01L23/66 ,  H01L29/04 ,  H01L29/16 ,  H01L21/762 ,  H01L21/02 ,  H01L27/13

CPC分类号： H01L21/763 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L23/66 ,  H01L27/13 ,  H01L29/04 ,  H01L29/16

摘要： The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.

公开(公告)号：US20150243548A1

公开(公告)日：2015-08-27

申请号：US14192728

申请日：2014-02-27

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Anthony Mark Miscione ,  James S. Cable

IPC分类号： H01L21/762 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L21/76251 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/6678 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78657

摘要： A method and structure for control of FET back-channel interface characteristics of an integrated circuit by implanting of selected implantation species at or near a device interface accessible during manufacture of the integrated circuit using layer transfer technology, without adversely affecting the structure or characteristics of a principal front-side FET.

摘要翻译： 一种通过在使用层转移技术在集成电路制造期间可访问的器件接口处或附近植入选定的植入物种来控制集成电路的FET背向通道接口特性的方法和结构，而不会不利地影响结构或特性 主要前端FET。