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    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING
    103.
    发明申请
    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING 有权

    公开(公告)号：US20220384724A1

    公开(公告)日：2022-12-01

    申请号：US17880835

    申请日：2022-08-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

    SWITCHING LAYER SCHEME TO ENHANCE RRAM PERFORMANCE
    104.
    发明申请
    SWITCHING LAYER SCHEME TO ENHANCE RRAM PERFORMANCE 有权

    公开(公告)号：US20220302381A1

    公开(公告)日：2022-09-22

    申请号：US17834115

    申请日：2022-06-07

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hai-Dang Trinh ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Wen-Ting Chu

    IPC: H01L45/00 ,  G06F12/02

    Abstract: The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.

    METAL LANDING ON TOP ELECTRODE OF RRAM
    105.
    发明申请
    METAL LANDING ON TOP ELECTRODE OF RRAM 有权

    公开(公告)号：US20220209111A1

    公开(公告)日：2022-06-30

    申请号：US17694913

    申请日：2022-03-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Wen-Ting Chu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

    RRAM BOTTOM ELECTRODE
    106.
    发明申请
    RRAM BOTTOM ELECTRODE 有权

    公开(公告)号：US20220085288A1

    公开(公告)日：2022-03-17

    申请号：US17533411

    申请日：2021-11-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

    IPC: H01L45/00

    Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

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