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公开(公告)号：US12171104B2
公开(公告)日：2024-12-17
申请号：US18336093
申请日：2023-06-16
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Fu-Chen Chang
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
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公开(公告)号：US20240379533A1
公开(公告)日：2024-11-14
申请号：US18316429
申请日：2023-05-12
Inventor： Tzu-Yu Chen , Wen-Ting Chu , Kuo-Chi Tu , Sheng-Hung Shih
IPC: H01L23/522 , H01L21/768 , H01L23/528 , H10B51/30
Abstract: Some embodiments relate to a method of forming an integrated chip, including forming a first wire level over a substrate; depositing an etch stop layer over the first wire level; etching the etch stop layer to form an opening over the first wire level; depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening; depositing a first conductive layer over the barrier layer and in the opening; performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer; depositing a data storage layer and a second conductive layer over the first conductive layer; and patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.
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公开(公告)号：US20240071455A1
公开(公告)日：2024-02-29
申请号：US18506177
申请日：2023-11-10
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Wen-Ting Chu , Yong-Shiuan Tsair
CPC classification number: G11C11/2259 , G11C11/223 , G11C11/2255 , G11C11/2257 , H01L29/516 , H10B51/30 , H10B51/40
Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.
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公开(公告)号：US11856797B2
公开(公告)日：2023-12-26
申请号：US17589278
申请日：2022-01-31
Inventor： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H10B63/00 , H01L29/66 , H10N70/00 , H10N70/20 , H01L21/265 , H01L21/266 , H01L29/08 , H01L29/78
CPC classification number: H10B63/30 , H01L21/266 , H01L21/26513 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H10N70/011 , H10N70/026 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/883 , H10N70/8833
Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.
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公开(公告)号：US20230017020A1
公开(公告)日：2023-01-19
申请号：US17572919
申请日：2022-01-11
Inventor： Tzu-Yu Chen , Sheng-Hung Shih , Fu-Chen Chang , Kuo-Chi Tu
IPC: H01L27/11507
Abstract: Various embodiments of the present disclosure are directed towards a memory cell in which an interfacial layer is on a bottom of a ferroelectric layer, between a bottom electrode and a ferroelectric layer. The interfacial layer is a different material than the bottom electrode and the ferroelectric layer and has a top surface with high texture uniformity compared to a top surface of the bottom electrode. The interfacial layer may, for example, be a dielectric, metal oxide, or metal that is: (1) amorphous; (2) monocrystalline; (3) crystalline with low grain size variation; (4) crystalline with a high percentage of grains sharing a common orientation; (5) crystalline with a high percentage of grains having a small grain size; or 6) any combination of the foregoing. It has been appreciated that such materials lead to high texture uniformity at the top surface of the interfacial layer.
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Patent Agency Ranking
公开(公告)号：US20210035993A1
公开(公告)日：2021-02-04
申请号：US16780418
申请日：2020-02-03
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
IPC: H01L27/11507 , G11C11/22 , H01L27/11504 , H01L49/02
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US20190259944A1
公开(公告)日：2019-08-22
申请号：US16398633
申请日：2019-04-30
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You , Wen-Ting Chu , Yu-Wen Liao
Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
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公开(公告)号：US09853213B2
公开(公告)日：2017-12-26
申请号：US15380170
申请日：2016-12-15
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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9.发明申请Resistive Switching Random Access Memory with Asymmetric Source and Drain 审中-公开具有不对称源和漏极的电阻式开关随机存取存储器公开(公告)号：US20170033159A1
公开(公告)日：2017-02-02
申请号：US15292964
申请日：2016-10-13
Inventor： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L27/24 , H01L29/78 , H01L21/266 , H01L29/66 , H01L21/265 , H01L45/00 , H01L29/08
CPC classification number: H01L27/2436 , H01L21/26513 , H01L21/266 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1625
Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.
Abstract translation: 电阻随机存取存储器（RRAM）结构包括形成在半导体衬底上并被设计用于数据存储的电阻存储元件。 电阻元件包括电阻材料层。 电阻元件还包括由电阻材料层插入的第一和第二电极。 电阻元件还包括形成在半导体衬底上并与电阻性存储元件耦合的场效应晶体管（FET），其中FET包括不对称源极和漏极，漏极具有比源高的掺杂浓度。 电阻存储元件与漏极耦合。
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10.发明授权Resistive switching random access memory with asymmetric source and drain 有权具有不对称源极和漏极的电阻式开关随机存取存储器公开(公告)号：US09478638B2
公开(公告)日：2016-10-25
申请号：US13795123
申请日：2013-03-12
Inventor： Chin-Chieh Yang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen
CPC classification number: H01L27/2436 , H01L21/26513 , H01L21/266 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1625
Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.
Abstract translation: 本公开提供了电阻随机存取存储器（RRAM）结构的一个实施例。 RRAM结构包括形成在半导体衬底上并被设计用于数据存储的电阻性存储元件; 和场效应晶体管（FET），形成在半导体衬底上并与电阻式存储元件耦合。 FET包括不对称源极和漏极。 电阻元件包括电阻材料层，并且还包括由电阻材料层插入的第一和第二电极。
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