公开(公告)号：US09997617B2

公开(公告)日：2018-06-12

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/765 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

公开(公告)号：US20160172456A1

公开(公告)日：2016-06-16

申请号：US14567925

申请日：2014-12-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Bin Yang ,  Jun Yuan ,  Yu Lu

IPC: H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

Abstract translation: 半导体器件包括具有金属栅极，源极和漏极的晶体管。 半导体器件还包括位于晶体管的金属栅极上方的高电阻金属蚀刻停止层。 半导体器件还包括形成在高电阻金属蚀刻停止层上的金属层。 金属层位于晶体管的源极或晶体管的漏极中的至少一个的上方。

公开(公告)号：US09349656B2

公开(公告)日：2016-05-24

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/47 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US20150221638A1

公开(公告)日：2015-08-06

申请号：US14690144

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20150162404A1

公开(公告)日：2015-06-11

申请号：US14100489

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/22 ,  H01L29/20 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0684 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

Abstract translation: 一种装置包括从第一蚀刻停止层的表面延伸的第一鳍状场效应晶体管（FinFET）器件。 该装置还包括从第二蚀刻停止层的表面延伸的第二FinFET器件。 第一化合物层介于第一蚀刻停止层和第二蚀刻停止层之间。

公开(公告)号：US20150036437A1

公开(公告)日：2015-02-05

申请号：US13957460

申请日：2013-08-02

Applicant: Qualcomm Incorporated

Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

IPC: G11C16/10 ,  H01L21/28 ,  H01L29/66

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

公开(公告)号：US20140219016A1

公开(公告)日：2014-08-07

申请号：US13759344

申请日：2013-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: G11C7/12 ,  G11C11/40 ,  G06F17/50

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract translation: 一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。 第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。 第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

公开(公告)号：US20140211546A1

公开(公告)日：2014-07-31

申请号：US13869110

申请日：2013-04-24

Applicant: Industry-Academic Cooperation Foundation, Yonsei University ,  QUALCOMM INCORPORATED

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

公开(公告)号：US20140197520A1

公开(公告)日：2014-07-17

申请号：US13743434

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  Bin Yang ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L28/24

Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.

Abstract translation: 在特定实施例中，一种方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露光学平坦化层的区域。 至少部分地在该区域内形成电阻层。 该方法还包括去除光学平坦化层的至少第二部分和电阻层的至少第三部分以形成电阻器。

公开(公告)号：US12057394B2

公开(公告)日：2024-08-06

申请号：US17410690

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Bin Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5226 ,  H01L21/76834 ,  H01L23/53295

Abstract: Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.