公开(公告)号：US20160247722A1

公开(公告)日：2016-08-25

申请号：US15143969

申请日：2016-05-02

Applicant: International Business Machines Corporation ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US09240375B2

公开(公告)日：2016-01-19

申请号：US13931692

申请日：2013-06-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H03H11/40 ,  H01L23/525 ,  H01F17/02 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract translation: 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。

公开(公告)号：US12207570B2

公开(公告)日：2025-01-21

申请号：US17655081

申请日：2022-03-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ching-Tzu Chen ,  Juntao Li ,  Kangguo Cheng ,  Carl Radens

IPC: H10N70/20 ,  H10B63/00 ,  H10B63/10 ,  H10N70/00

Abstract: A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.

公开(公告)号：US20240196586A1

公开(公告)日：2024-06-13

申请号：US18063956

申请日：2022-12-09

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Carl Radens ,  Ruilong Xie

IPC: H10B10/00

CPC classification number: H01L27/1108 ,  H01L27/1116

Abstract: A semiconductor structure is provided that includes a stacked transistor including at least one transistor stacked over another transistor and a non-stacked transistor integrated on a same wafer. Both the stacked transistor and the non-stacked transistor include frontside and backside interconnects.

公开(公告)号：US20240172408A1

公开(公告)日：2024-05-23

申请号：US17991243

申请日：2022-11-21

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Ruilong Xie ,  Junli Wang ,  Carl Radens

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78

CPC classification number: H10B10/125 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B10/12 ,  H01L29/66795 ,  H01L29/785

Abstract: A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

公开(公告)号：US20240155822A1

公开(公告)日：2024-05-09

申请号：US18053451

申请日：2022-11-08

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruilong Xie ,  Albert M. Chu ,  Carl Radens

IPC: H01L27/11 ,  H01L23/48

CPC classification number: H01L27/1104 ,  H01L23/481

Abstract: A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

公开(公告)号：US20240088146A1

公开(公告)日：2024-03-14

申请号：US17931319

申请日：2022-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M. Chu ,  Carl Radens ,  Brent A. Anderson

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region. A middle section contact is located in the middle gate cut region.

公开(公告)号：US20240079316A1

公开(公告)日：2024-03-07

申请号：US17903644

申请日：2022-09-06

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Albert M. Chu ,  Carl Radens ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L21/74 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L23/481 ,  H01L23/5286

Abstract: A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

公开(公告)号：US11791199B2

公开(公告)日：2023-10-17

申请号：US17406351

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Carl Radens

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66545

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

公开(公告)号：US11645206B2

公开(公告)日：2023-05-09

申请号：US17472764

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ahmet Serkan Ozcan ,  Tomasz Kornuta ,  Carl Radens ,  Nicolas Antoine

IPC: G06F16/00 ,  G06F16/2453 ,  G06F12/02 ,  G06F12/0817 ,  G06F16/33 ,  G06N3/063 ,  G11C11/4076 ,  G11C11/4093 ,  G06F16/2458 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0824 ,  G06F12/0246 ,  G06F16/3347 ,  G06N3/063 ,  G11C11/4076 ,  G11C11/4093 ,  G06F3/067 ,  G06F12/06 ,  G06F16/2458 ,  G06F16/24545

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.