公开(公告)号：US20130105914A1

公开(公告)日：2013-05-02

申请号：US13281448

申请日：2011-10-26

Applicant: Chien-Ting Lin

Inventor： Chien-Ting Lin

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.

Abstract translation: 制造具有翅片结构的场效应晶体管的方法包括以下步骤。 提供了具有第一导电类型的离子阱的衬底，其中离子阱具有第一掺杂浓度。 至少形成设置在基板上的翅片结构。 至少进行第一离子注入以在衬底和沟道层之间形成具有第一导电类型的抗冲击掺杂区域，其中抗冲击掺杂区域具有高于第一掺杂浓度的第三掺杂浓度。 在执行第一离子注入之后，形成沿鳍片结构的至少一个表面设置的至少一个沟道层。 形成覆盖翅片结构的一部分的栅极。 形成在栅极旁边的翅片结构中设置的源极和漏极，其中源极和漏极具有第二导电类型。

公开(公告)号：US20130087832A1

公开(公告)日：2013-04-11

申请号：US13253375

申请日：2011-10-05

Applicant: Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

Inventor： Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Abstract translation: 在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构 。 嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。 半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。 还提供了形成上述装置的方法。

公开(公告)号：US20130083567A1

公开(公告)日：2013-04-04

申请号：US13551769

申请日：2012-07-18

Applicant: Tadahiro Imada

Inventor： Tadahiro Imada

IPC: H01L29/772 ,  H02M5/458 ,  H01L21/20

CPC classification number: H01L29/41725 ,  H01L23/4824 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A compound semiconductor device includes an electron transit layer having a first polarity, a p-type cap layer which is formed above the electron transit layer and has a second polarity, and an n-type cap layer which is formed on the p-type cap layer and has the first polarity. The n-type cap layer includes portions having different thicknesses.

Abstract translation: 化合物半导体器件包括具有第一极性的电子转移层，形成在电子转移层上方并具有第二极性的p型帽层，以及形成在p型帽上的n型帽层 并具有第一极性。 n型盖层包括具有不同厚度的部分。

公开(公告)号：US20130082242A1

公开(公告)日：2013-04-04

申请号：US13251637

申请日：2011-10-03

Applicant: Shu-Jen Han ,  Alberto Valdes Garcia

Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

IPC: H01L29/772 ,  H01L21/336 ,  H01L29/775 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78636 ,  H01L29/78684

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

公开(公告)号：US20130075833A1

公开(公告)日：2013-03-28

申请号：US13239804

申请日：2011-09-22

Applicant: Kuan-Ting Liu ,  Liang-Gi Yao ,  Yasutoshi Okuno ,  Clement Hsingjen Wann

Inventor： Kuan-Ting Liu ,  Liang-Gi Yao ,  Yasutoshi Okuno ,  Clement Hsingjen Wann

IPC: H01L29/772

CPC classification number: H01L21/823842 ,  H01L21/28008 ,  H01L21/28079 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

Abstract translation: 公开了一种多层扫气金属栅叠层及其制造方法。 在一个示例中，设置在半导体衬底上的栅极堆叠包括设置在半导体衬底上的界面电介质层，设置在界面电介质层上的高k电介质层，设置在高k电介质层上的第一导电层，以及 设置在所述第一导电层上的第二导电层。 第一导电层包括设置在高k电介质层上的第一金属层，设置在第一金属层上的第二金属层和设置在第二金属层上的第三金属层。 第一金属层包括从界面电介质层清除氧杂质的材料，第二金属层包括从第三金属层吸附氧杂质并防止氧杂质扩散到第一金属层中的材料。

公开(公告)号：US20130069121A1

公开(公告)日：2013-03-21

申请号：US13701129

申请日：2011-05-18

Applicant: Atsuhito Murai ,  Yoshiharu Kataoka ,  Takuya Watanabe ,  Yuhko Hisada ,  Satoshi Horiuchi

Inventor： Atsuhito Murai ,  Yoshiharu Kataoka ,  Takuya Watanabe ,  Yuhko Hisada ,  Satoshi Horiuchi

IPC: H01L29/772

CPC classification number: G01N27/4148

Abstract: The present invention provides an ion sensor with which an ion concentration in a sample in which both ions are mixed can be measured with high accuracy, a display device, a method for driving the ion sensor, and a method for calculating an ion concentration. The present invention is an ion sensor that includes a field effect transistor. The ion sensor detects one of negative ions and positive ions using the field effect transistor, and consecutively thereafter detects the other of the negative ions and positive ions using the field effect transistor.

Abstract translation: 本发明提供了一种离子传感器，其中可以高精度地测量两个离子混合的样品中的离子浓度，显示装置，用于驱动离子传感器的方法和离子浓度计算方法。 本发明是一种包括场效应晶体管的离子传感器。 离子传感器使用场效应晶体管检测负离子和正离子之一，然后使用场效应晶体管连续检测另一个负离子和正离子。

公开(公告)号：US20130069111A1

公开(公告)日：2013-03-21

申请号：US13235211

申请日：2011-09-16

Applicant: Stefan Flachowsky ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

Abstract translation: 提供应变半导体器件的实施例，如制造这种应变半导体器件的方法的实施例。 在一个实施例中，该方法包括提供部分制造的半导体器件，其包括具有源极侧和漏极侧的半导体衬底，形成在半导体衬底上的栅极叠层以及形成在栅叠层下方的半导体衬底内的沟道区，以及 从半导体衬底的源极侧向漏极侧延伸。 在半导体衬底的源极侧和漏极侧仅产生空腔，并且在空腔内形成应变诱导材料，以在半导体衬底内形成不对称的异质结结构。

公开(公告)号：US20130037823A1

公开(公告)日：2013-02-14

申请号：US13403177

申请日：2012-02-23

Applicant: Takahisa Kanemura ,  Masaki Kondo

Inventor： Takahisa Kanemura ,  Masaki Kondo

IPC: H01L29/772

CPC classification number: H01L29/7391 ,  H01L21/8213 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/0814 ,  H01L27/092 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42312 ,  H01L29/66356

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract translation: 在一个实施例中，半导体器件包括半导体衬底，经由绝缘层设置在半导体衬底上的栅电极和设置在栅电极的侧表面上的栅极绝缘体。 该器件包括层叠层，该堆叠层包括依次堆叠在半导体衬底上的第一导电类型的下主要主端子层，中间层和第二导电类型的上主端子层，堆叠层设置在侧面 通过栅极绝缘体的栅电极的表面。 上或下主端子层经由栅极绝缘体和半导体层设置在栅电极的侧表面上。

公开(公告)号：US20130032854A1

公开(公告)日：2013-02-07

申请号：US13136348

申请日：2011-08-01

Applicant: Chao-Cheng LUI

Inventor： Chao-Cheng LUI

IPC: H01L29/772

CPC classification number: H03K17/6874

Abstract: The rectifier in this invention is connected in series with two field effect transistor, comprises: the source S1 of first N-channel FET F1 and the source S2 of second N-channel FET F2 are directly connected together, the gate G1 of first N-channel FET F1 and the gate G2 of second N-channel FET F2 are connected together form a control terminal GA, the drain D1 of first N-channel FET F1 form a input terminal D1, the drain D2 of second N-channel FET F2 form a output terminal D2, the body diode DA of first N-channel FET F1 and the body diode DB of second N-channel FET F2, are back-to-back series connected together, the right side equivalent circuit F are first N-channel FET F1 and second N-channel FET F2 equivalent circuit, form a rectifier F of the present invention.

Abstract translation: 本发明的整流器与两个场效应晶体管串联连接，包括：第一N沟道FET F1的源极S1和第二N沟道FET F2的源极S2直接连接在一起，第一N-沟道FET的栅极G1， 通道FET F1和第二N沟道FET F2的栅极G2一起形成控制端子GA，第一N沟道FET F1的漏极D1形成输入端子D1，第二N沟道FET F2的漏极D2形成 输出端子D2，第一N沟道FET F1的体二极管DA和第二N沟道FET F2的体二极管DB是背对背串联连接的，右侧等效电路F是第一N沟道 FET F1和第二N沟道FET F2等效电路，形成本发明的整流器F.

公开(公告)号：US08368084B2

公开(公告)日：2013-02-05

申请号：US12876598

申请日：2010-09-07

Applicant: Kentaro Ikeda ,  Masahiko Kuraguchi

Inventor： Kentaro Ikeda ,  Masahiko Kuraguchi

IPC: H01L29/772

CPC classification number: H01L27/0605 ,  H01L27/0629 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7786

Abstract: In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer.

Abstract translation: 在一个实施例中，提供了一种半导体器件，其中常导型FET; 电容器，其一个电极与FET的栅极电连接，另一个电极与输入端电连接; 并且在与FET的栅极电连接的阳极电极和与FET的源极电连接的阴极电极的二极管形成在形成有FET的同一芯片上。 此外，电容器可以具有其中在FET的栅极拉制电极上形成诸如电介质的绝缘膜的结构，并且在绝缘层上形成金属层。