公开(公告)号：US09490344B2

公开(公告)日：2016-11-08

申请号：US13345922

申请日：2012-01-09

Applicant: Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC: H01L21/02 ,  H01L21/334 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

Abstract translation: 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。

公开(公告)号：US08703578B2

公开(公告)日：2014-04-22

申请号：US13482410

申请日：2012-05-29

Applicant: Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

Inventor： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L21/76

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0883 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.

Abstract translation: 提供具有PMOS eSiGe源极/漏极区域的HKMG器件。 实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并且在第二HKMG栅堆叠的相对侧形成深源极/漏极区域 第二个HKMG门栈。

公开(公告)号：US20130302956A1

公开(公告)日：2013-11-14

申请号：US13470454

申请日：2012-05-14

Applicant: Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.

Abstract translation: 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬底层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。

公开(公告)号：US08574981B2

公开(公告)日：2013-11-05

申请号：US13101659

申请日：2011-05-05

Applicant: Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka ,  Jan Hoentschel

IPC: H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66431 ,  H01L29/66651 ,  H01L29/7781 ,  H01L29/7833

Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.

Abstract translation: 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度 在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。

公开(公告)号：US08563374B2

公开(公告)日：2013-10-22

申请号：US13235211

申请日：2011-09-16

Applicant: Stefan Flachowsky ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

Abstract translation: 提供应变半导体器件的实施例，如制造这种应变半导体器件的方法的实施例。 在一个实施例中，该方法包括提供部分制造的半导体器件，其包括具有源极侧和漏极侧的半导体衬底，形成在半导体衬底上的栅极叠层以及形成在栅叠层下方的半导体衬底内的沟道区，以及 从半导体衬底的源极侧向漏极侧延伸。 在半导体衬底的源极侧和漏极侧仅产生空腔，并且在空腔内形成应变诱导材料，以在半导体衬底内形成不对称的异质结结构。

公开(公告)号：US08524563B2

公开(公告)日：2013-09-03

申请号：US13345457

申请日：2012-01-06

Applicant: Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

Abstract translation: 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

公开(公告)号：US20120309182A1

公开(公告)日：2012-12-06

申请号：US13118826

申请日：2011-05-31

Applicant: Stefan Flachowsky ,  Jan Hoentschel ,  Peter Javorka

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Peter Javorka

IPC: H01L21/3205 ,  B82Y40/00

CPC classification number: H01L21/823425 ,  H01L21/823468 ,  H01L29/66659

Abstract: Disclosed herein is a method of forming sidewall spacers for a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate. performing a non-conformal deposition process to deposit a layer of spacer material above the gate electrode structure and performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer proximate a first side of the gate electrode structure and a second sidewall spacer proximate a second side of the gate electrode structure, wherein the first and second sidewall spacers have different widths.

Abstract translation: 这里公开了一种形成半导体器件的侧壁间隔物的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构。 执行非共形沉积工艺以在栅极电极结构上方沉积间隔物材料层，并对间隔物材料层进行各向异性蚀刻工艺以限定靠近栅电极结构的第一侧的第一侧壁间隔物，以及第二侧壁 靠近栅电极结构的第二侧的间隔件，其中第一和第二侧壁间隔件具有不同的宽度。

公开(公告)号：US08062952B2

公开(公告)日：2011-11-22

申请号：US12784819

申请日：2010-05-21

Applicant: Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

IPC: H01L21/30

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7846

Abstract: In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.

Abstract translation: 在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变 相应活性区的比例。 已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。 因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。 另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。

公开(公告)号：US08962429B2

公开(公告)日：2015-02-24

申请号：US13572343

申请日：2012-08-10

Applicant: Stefan Flachowsky ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336

CPC classification number: H01L21/823418 ,  H01L21/823468

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括同时屏蔽半导体衬底的屏蔽区域并暴露半导体衬底的屏蔽区域的表面。 执行离子注入以在与屏蔽区域相邻的半导体衬底的非屏蔽区域中形成注入区域。 此外，半导体衬底被硅化以在半导体衬底的屏蔽区域中形成硅化区域。

公开(公告)号：US08872272B2

公开(公告)日：2014-10-28

申请号：US13545624

申请日：2012-07-10

Applicant: Stefan Flachowsky ,  Jan Hoentschel

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/31 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L27/092

Abstract: A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.

Abstract translation: 制造应力增强型CMOS电路的方法包括以第一间距形成第一多个MOS晶体管，并以第二间距形成第二多个MOS晶体管。 第二间距大于第一间距。 该方法还包括沉积覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是沉积在应力增强CMOS电路制造中的唯一应力衬垫。 应力增强型CMOS电路包括以第一间距形成的第一多个MOS晶体管和以第二间距形成的第二多个MOS晶体管。 第二间距大于第一间距。 电路还包括覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是在应力增强CMOS电路上形成的唯一应力衬垫。