Invention Application
- Patent Title: MULTI-LAYER SCAVENGING METAL GATE STACK FOR ULTRA-THIN INTERFACIAL DIELCTRIC LAYER
- Patent Title (中): 用于超薄界面层压层的多层金属栅极叠层
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Application No.: US13239804Application Date: 2011-09-22
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Publication No.: US20130075833A1Publication Date: 2013-03-28
- Inventor: Kuan-Ting Liu , Liang-Gi Yao , Yasutoshi Okuno , Clement Hsingjen Wann
- Applicant: Kuan-Ting Liu , Liang-Gi Yao , Yasutoshi Okuno , Clement Hsingjen Wann
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L29/772
- IPC: H01L29/772

Abstract:
A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.
Public/Granted literature
- US08766379B2 Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer Public/Granted day:2014-07-01
Information query
IPC分类: