公开(公告)号：US08148217B2

公开(公告)日：2012-04-03

申请号：US13099587

申请日：2011-05-03

Applicant: Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

Inventor： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/78609

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract translation: 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US20110207309A1

公开(公告)日：2011-08-25

申请号：US13099587

申请日：2011-05-03

Applicant: Takashi IZUMIDA ,  Sanae Ito ,  Takahisa Kanemura

Inventor： Takashi IZUMIDA ,  Sanae Ito ,  Takahisa Kanemura

IPC: H01L21/28

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/78609

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract translation: 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US20110121381A1

公开(公告)日：2011-05-26

申请号：US12719193

申请日：2010-03-08

Applicant: Takahisa KANEMURA ,  Tomomi KUSAKA ,  Takashi IZUMIDA ,  Masaki KONDO ,  Nobutoshi AOKI

Inventor： Takahisa KANEMURA ,  Tomomi KUSAKA ,  Takashi IZUMIDA ,  Masaki KONDO ,  Nobutoshi AOKI

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

Abstract translation: 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅极绝缘体上的第一浮动栅极，第二栅极绝缘体 形成在第一浮栅上并用作FN隧道膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US07842998B2

公开(公告)日：2010-11-30

申请号：US12248449

申请日：2008-10-09

Applicant: Takahisa Kanemura ,  Takashi Izumida ,  Nobutoshi Aoki

Inventor： Takahisa Kanemura ,  Takashi Izumida ,  Nobutoshi Aoki

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.

Abstract translation: 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：半导体衬底; 串联连接的存储单元晶体管; 以及选择晶体管，其包括：在所述存储单元晶体管的一端形成在所述半导体衬底中的第一扩散区域; 在所述第一扩散区域的一侧形成在所述半导体基板上的第一绝缘膜; 形成在所述第一绝缘膜上的选择栅电极; 形成为从半导体衬底向上延伸并与选择栅电极分离的半导体柱; 形成在选择栅电极和半导体柱之间的第二绝缘膜; 以及形成在所述半导体柱上的第二扩散区域。

公开(公告)号：US07662679B2

公开(公告)日：2010-02-16

申请号：US11203425

申请日：2005-08-15

Applicant: Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

Inventor： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/78609

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract translation: 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US08575624B2

公开(公告)日：2013-11-05

申请号：US13403177

申请日：2012-02-23

Applicant: Takahisa Kanemura ,  Masaki Kondo

Inventor： Takahisa Kanemura ,  Masaki Kondo

IPC: H01L29/15

CPC classification number: H01L29/7391 ,  H01L21/8213 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/0814 ,  H01L27/092 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42312 ,  H01L29/66356

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract translation: 在一个实施例中，半导体器件包括半导体衬底，经由绝缘层设置在半导体衬底上的栅电极和设置在栅电极的侧表面上的栅极绝缘体。 该器件包括层叠层，该堆叠层包括依次堆叠在半导体衬底上的第一导电类型的下主要主端子层，中间层和第二导电类型的上主端子层，堆叠层设置在侧面 通过栅极绝缘体的栅电极的表面。 上或下主端子层经由栅极绝缘体和半导体层设置在栅电极的侧表面上。

公开(公告)号：US20130037823A1

公开(公告)日：2013-02-14

申请号：US13403177

申请日：2012-02-23

Applicant: Takahisa Kanemura ,  Masaki Kondo

Inventor： Takahisa Kanemura ,  Masaki Kondo

IPC: H01L29/772

CPC classification number: H01L29/7391 ,  H01L21/8213 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/0814 ,  H01L27/092 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42312 ,  H01L29/66356

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract translation: 在一个实施例中，半导体器件包括半导体衬底，经由绝缘层设置在半导体衬底上的栅电极和设置在栅电极的侧表面上的栅极绝缘体。 该器件包括层叠层，该堆叠层包括依次堆叠在半导体衬底上的第一导电类型的下主要主端子层，中间层和第二导电类型的上主端子层，堆叠层设置在侧面 通过栅极绝缘体的栅电极的表面。 上或下主端子层经由栅极绝缘体和半导体层设置在栅电极的侧表面上。

公开(公告)号：US08258562B2

公开(公告)日：2012-09-04

申请号：US12470030

申请日：2009-05-21

Applicant: Takashi Izumida ,  Takahisa Kanemura ,  Nobutoshi Aoki

Inventor： Takashi Izumida ,  Takahisa Kanemura ,  Nobutoshi Aoki

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

Abstract translation: 本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。 选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分 选择栅极晶体管。

公开(公告)号：US08212306B2

公开(公告)日：2012-07-03

申请号：US12721757

申请日：2010-03-11

Applicant: Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

Inventor： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

Abstract translation: 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

公开(公告)号：US6099574A

公开(公告)日：2000-08-08

申请号：US991406

申请日：1997-12-16

Applicant: Sanae Fukuda ,  Hirotaka Amakawa ,  Takahisa Kanemura

Inventor： Sanae Fukuda ,  Hirotaka Amakawa ,  Takahisa Kanemura

IPC: H01L29/00 ,  G06F17/50 ,  H01L21/00 ,  H01L21/02 ,  H01L21/265 ,  G06F9/455

CPC classification number: G06F17/5018

Abstract: Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices. The process simulation results are used directly as input to device simulation, to rapidly obtain performance of semiconductor devices such as current vs voltage characteristics. Therefore, the efficiency of calculations required to obtain the optimal conditions for semiconductor structures can be improved, thus shortening the lapse of time for designing and development of semiconductor devices.

Abstract translation: LSI和其他半导体器件的工艺仿真将处理作为不同杂质在不同工艺中引入的多种相同的杂质。 因此，通过在计算中将它们处理为不同的杂质，可以获得半导体器件中的杂质的分布特征，而不受另一过程中引入的另一相同杂质的影响或处理过程中的多个工艺的影响。 因此，甚至讨论了多个工艺条件，或者当半导体器件制造工艺的序列中的一个或一些工艺在过程中被改变时，不需要从 开始。 并且可以容易地确定在基于最终获得的半导体器件的结构的条件下必须改变哪个工艺。 过程仿真结果直接用作器件仿真的输入，以快速获得半导体器件的性能，如电流与电压特性。 因此，可以提高获得半导体结构的最佳条件所需的计算效率，从而缩短半导体器件的设计和开发时间的流逝。