公开(公告)号：US20160240613A1

公开(公告)日：2016-08-18

申请号：US15136048

申请日：2016-04-22

申请人： International Business Machines Corporation

发明人： Cheng-Wei Cheng ,  Effendi Leobandung ,  Devendra K. Sadana

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311

CPC分类号： H01L29/0673 ,  H01L21/02233 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/845 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78696

摘要： Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

摘要翻译： 本发明的实施例提供了制造具有选择氧化的半导体器件的方法。 一种方法可以包括提供包括两个半导体层的堆叠的半导体衬底; 在半导体衬底上沉积绝缘材料; 形成一组翅片; 选择性地氧化半导体层之一; 沿着虚拟栅极结构的侧面形成一个虚拟栅极结构和一组间隔物; 形成与所述虚拟栅极结构相邻的源极极区; 去除虚拟栅极结构; 并释放选择性氧化的半导体层。

公开(公告)号：US09412856B2

公开(公告)日：2016-08-09

申请号：US14474028

申请日：2014-08-29

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hidetoshi Fujimoto

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02

CPC分类号： H01L29/7786 ,  H01L21/02241 ,  H01L29/1066 ,  H01L29/2003

摘要： A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers.

摘要翻译： 半导体器件包括第一和第二氮化物半导体层。 第二氮化物半导体层具有比第一氮化物半导体层更大的带隙。 源电极和漏电极在第二氮化物半导体层上形成为彼此间隔开。 在源极和漏极之间的第二氮化物半导体层上形成第三氮化物半导体层。 在第三氮化物半导体层上形成栅电极。 第三氮化物半导体层包括至少两个第一层和至少一个第二层，其具有比第一层低的p型掺杂剂浓度。 第二层也具有比第一层大的带隙。 第三氮化物半导体层堆叠中的最下层和最上层是第一层。

公开(公告)号：US20160163802A1

公开(公告)日：2016-06-09

申请号：US14906713

申请日：2013-08-23

申请人： INTEL CORPORATION

发明人： GLENN A. GLASS ,  ANAND S. MURTHY

IPC分类号： H01L29/205 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L21/02

CPC分类号： H01L29/205 ,  H01L21/02241 ,  H01L21/02247 ,  H01L21/02373 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76264 ,  H01L27/0255 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.

摘要翻译： 公开了在用于诸如金属氧化物半导体（MOS）晶体管的半导体器件的III-V沟道层和IV族衬底之间使用高电阻层的技术。 可以使用高电阻层来最小化（或消除）电流从源极到漏极的流动，其不同于直接通过通道的路径。 在一些情况下，高电阻层可以是III-V宽带隙层。 在一些这种情况下，宽带隙层可具有大于1.4电子伏（eV）的带隙，并且甚至可以具有大于2.0eV的带隙。 在其他情况下，例如，宽带隙层可以通过氧化或氮化部分或完全转变为绝缘体。 所得到的结构可以与平面，翅片或纳米线/纳米级晶体管架构一起使用以帮助防止衬底泄漏问题。

公开(公告)号：US20160064540A1

公开(公告)日：2016-03-03

申请号：US14935346

申请日：2015-11-06

申请人： Intel Corporation

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/205

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US09257535B2

公开(公告)日：2016-02-09

申请号：US14725719

申请日：2015-05-29

申请人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

发明人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  B82Y10/00

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02241 ,  H01L21/02603 ,  H01L21/30612 ,  H01L21/30635 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7841 ,  H01L29/78696

摘要： A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.

公开(公告)号：US20160020313A1

公开(公告)日：2016-01-21

申请号：US14542937

申请日：2014-11-17

申请人： Transphorm Inc.

发明人： Mo Wu ,  Rakesh K. Lal ,  Ilan Ben-Yaacov ,  Umesh Mishra ,  Carl Joseph Neufeld

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/28264 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/31144 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

摘要： A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

摘要翻译： 制造III-N器件的方法包括在衬底上形成III-N沟道层，在沟道层上形成III-N势垒层，在阻挡层上形成绝缘体层，在器件的第一部分形成沟槽 。 形成沟槽包括在器件的第一部分中去除绝缘体层和阻挡层的一部分，使得器件的第一部分中的阻挡层的剩余部分具有远离通道的顶表面的厚度 层，厚度在预定厚度范围内，在包括氧气的气体环境中在升高的温度下退火III-N器件以氧化器件的第一部分中的阻挡层的剩余部分，并且去除氧化的剩余部分 在装置的第一部分中的阻挡层。

公开(公告)号：US20150364320A1

公开(公告)日：2015-12-17

申请号：US14686488

申请日：2015-04-14

申请人： MAJID RIAZIAT

发明人： MAJID RIAZIAT

IPC分类号： H01L21/02

CPC分类号： H01L21/02241 ,  H01L21/67 ,  H01L21/67017 ,  H01S5/18311

摘要： Wafer oxidation apparatus for selective oxidation of a semiconductor workpiece has an oxidation chamber. The oxidation chamber is heated by external infrared heating lamps. A chuck assembly is disposed within the oxidation chamber and configured to be approximately thermally isolated from the oxidation chamber. Carrier gas pathways deliver heated carrier gasses to the oxidation chamber at variable rates for oxidation uniformity.

摘要翻译： 用于半导体工件的选择性氧化的晶片氧化装置具有氧化室。 氧化室由外部红外加热灯加热。 卡盘组件设置在氧化室内并被构造成与氧化室近似热隔离。 载气通道以可变的速率将加热的载气气体输送到氧化室以获得氧化均匀性。

公开(公告)号：US20150349107A1

公开(公告)日：2015-12-03

申请号：US14721796

申请日：2015-05-26

申请人： DELTA ELECTRONICS, INC.

发明人： Wen-Chia LIAO

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/66462 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28264 ,  H01L21/31105 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787

摘要： A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

摘要翻译： 半导体器件包括衬底，沟道层，间隔层，阻挡层和氧化覆盖层。 沟道层设置在衬底上或衬底上。 间隔层设置在沟道层上。 阻挡层设置在间隔层上。 氧化的盖层设置在阻挡层上。 氧化盖层由氮氧化物制成。

公开(公告)号：US20150171205A1

公开(公告)日：2015-06-18

申请号：US14630541

申请日：2015-02-24

申请人： Intel Corporation

发明人： HAN WUI THEN ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/205

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：US20140306181A1

公开(公告)日：2014-10-16

申请号：US14251717

申请日：2014-04-14

申请人： LG ELECTRONICS INC.

发明人： Jonghoon SHIN ,  Woongsun KIM ,  Taehoon JANG

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/7783 ,  H01L21/02241 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： This specification relates to an enhancement-type semiconductor device having a passivation layer formed using a photoelectrochemical (PEC) method, and a fabricating method thereof. To this end, a semiconductor device according to one exemplary embodiment includes a GaN layer, an AlGaN layer formed on the GaN layer, a p-GaN layer formed on the AlGaN layer, a gate electrode formed on the p-GaN layer, a source electrode and a drain electrode formed on a partial region of the AlGaN layer, and a passivation layer formed on a partial region of the AlGaN layer, the passivation layer formed between the source electrode and the gate electrode or between the gate electrode and the drain electrode, wherein the passivation layer is formed in a manner of oxidizing a part of the p-GaN layer. DC 51111930.1

摘要翻译： 本说明书涉及具有使用光电化学（PEC）方法形成的钝化层的增强型半导体器件及其制造方法。 为此，根据一个示例性实施例的半导体器件包括GaN层，形成在GaN层上的AlGaN层，在AlGaN层上形成的p-GaN层，形成在p-GaN层上的栅电极，源极 电极和形成在AlGaN层的部分区域上的漏电极，以及形成在所述AlGaN层的部分区域上的钝化层，所述钝化层形成在所述源电极和所述栅电极之间或所述栅电极与所述漏电极之间 ，其中所述钝化层以氧化所述p-GaN层的一部分的方式形成。 DC 51111930.1