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167 条记录 (耗时 0.023 秒)

    Method For Integrated Circuit Patterning
    91.
    发明申请
    Method For Integrated Circuit Patterning 有权
    集成电路图案化方法

    公开(公告)号：US20150147886A1

    公开(公告)日：2015-05-28

    申请号：US14088569

    申请日：2013-11-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Szu-Ping Tung ,  Huang-Yi Huang ,  Neng-Jye Yang ,  Ching-Hua Hsieh

    IPC分类号： H01L21/033

    CPC分类号： H01L21/0338 ,  C23G1/02 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32134

    摘要： A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate.

    摘要翻译： 形成目标图案的方法包括在第一掩模上在衬底上形成多条线，并在衬底上，多条线上以及多条线的侧壁上形成间隔层。 该方法还包括去除间隔层的至少一部分以暴露多条线和基底。 该方法还包括收缩设置在多条线的侧壁上的间隔层，并且去除多条线，从而在衬底上形成图案化间隔层。

    INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME
    93.
    发明申请
    INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME 有权
    互连结构及其形成方法

    公开(公告)号：US20150061141A1

    公开(公告)日：2015-03-05

    申请号：US14019276

    申请日：2013-09-05

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Szu-Ping Tung ,  Huang-Yi Huang ,  Wen-Jiun Liu ,  Ching-Hua Hsieh ,  Minghsing Tsai

    IPC分类号： H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76834 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.

    摘要翻译： 公开了一种半导体器件，互连结构及其形成方法。 一个实施例是一种形成半导体器件的方法，所述方法包括在衬底上形成第一介电层，在第一介电层中形成第一导电层，以及去除第一导电层的第一部分以形成至少两个导电 在第一电介质层中的线，所述至少两个导线被第一间隔分开。 该方法还包括在至少两条导电线上形成覆盖层，并且在覆盖层和第一介电层上形成蚀刻停止层。

    Package system and manufacturing method thereof
    98.
    发明授权
    Package system and manufacturing method thereof 有权

    公开(公告)号：US12040247B2

    公开(公告)日：2024-07-16

    申请号：US17320198

    申请日：2021-05-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang

    IPC分类号： H01L23/36 ,  H01L21/50 ,  H01L23/40

    CPC分类号： H01L23/36 ,  H01L21/50 ,  H01L23/40

    摘要： A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.