公开(公告)号：US09484351B2

公开(公告)日：2016-11-01

申请号：US14182952

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract translation: 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US09431413B2

公开(公告)日：2016-08-30

申请号：US14547251

申请日：2014-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/115 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L27/11563 ,  H01L21/28008 ,  H01L21/76229 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/4234 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

Abstract translation: 本发明涉及用于在嵌入式闪存HKMG集成电路上减少接触过蚀刻和高接触电阻（Rc）的结构和方法。 在一个实施例中，存储器接触焊盘区域下面的STI区域是凹进的，以使STI表面与半导体衬底的其余部分基本上共面。 该凹槽允许形成更厚的记忆接触垫结构。 这些接触焊盘结构上较厚的多晶硅防止接触过蚀刻，从而减少形成在其上的触点的Rc。

公开(公告)号：US20160225776A1

公开(公告)日：2016-08-04

申请号：US14609575

申请日：2015-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chin-Yi Huang ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L27/11507 ,  H01L21/28273 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/66825

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Abstract translation: 本公开涉及用于嵌入式闪存器件的集成电路（IC）。 在一些实施例中，IC包括存储器阵列区域和围绕设置在半导体衬底上的存储器阵列区域的边界区域。 在包括多个离散部分的存储器阵列区域处设置硬掩模。 硬掩模设置在存储器阵列区域的控制介质层的下方。

公开(公告)号：US09397112B1

公开(公告)日：2016-07-19

申请号：US14645993

申请日：2015-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/108 ,  H01L27/115 ,  H01L49/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332

Abstract: The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.

Abstract translation: 本公开涉及一种包括设置在电极之间的电荷捕获介电层的非平面FEOL（前端线）电容器和相关的制造方法。 在一些实施例中，非平面FEOL电容器具有设置在衬底上的第一电极。 电荷捕获电介质层在与第一电极相邻的位置处设置在基板上。 电荷俘获介电层具有“L”形状，其中侧向分量沿第一方向延伸，垂直分量沿第二方向延伸。 第二电极布置在侧向部件上并且通过第一部件与第一电极分离。

公开(公告)号：US20150279849A1

公开(公告)日：2015-10-01

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20140264725A1

公开(公告)日：2014-09-18

申请号：US13854507

申请日：2013-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract translation: 所描述的实施例提供了用于蚀刻半导体主体上的有源区域并且外延沉积覆盖有源区域的半导体层的方法和半导体器件区域。 这些方法可以减轻或消除随后与STI科技相关的制造过程中遇到的问题。

公开(公告)号：US11569443B2

公开(公告)日：2023-01-31

申请号：US16935139

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating the semiconductor device is provided. The method includes depositing a first dielectric layer; forming a first memory cell over the first dielectric layer; depositing a second dielectric layer over the first memory cell; and forming a second memory cell over the second dielectric layer. Forming the first memory cell includes depositing a first resistance switching layer over the first dielectric layer and performing a first physical etching process to pattern the first resistance switching layer into a first resistance switching element. Forming the second memory cell includes depositing a second resistance switching layer over the second dielectric layer and performing a chemical etching process to pattern the second resistance switching layer into a second resistance switching element.

公开(公告)号：US20220285382A1

公开(公告)日：2022-09-08

申请号：US17826503

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US11437433B2

公开(公告)日：2022-09-06

申请号：US16930481

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L43/12 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L43/02

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.

公开(公告)号：US11283009B2

公开(公告)日：2022-03-22

申请号：US16702137

申请日：2019-12-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Chun-Heng Liao ,  Jun-Yao Chen ,  Hung-Cho Wang

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.