公开(公告)号：US20200152587A1

公开(公告)日：2020-05-14

申请号：US16733609

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L25/03 ,  H01L25/00 ,  H01L23/498 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  H01L25/065

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

公开(公告)号：US10312203B2

公开(公告)日：2019-06-04

申请号：US15625678

申请日：2017-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yung-Ping Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Yi-Che Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20190139787A1

公开(公告)日：2019-05-09

申请号：US15832742

申请日：2017-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yao-Tong Lai

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

公开(公告)号：US10283470B2

公开(公告)日：2019-05-07

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US20190131261A1

公开(公告)日：2019-05-02

申请号：US16233218

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  H01L25/10 ,  H01L21/56 ,  H01L25/00 ,  H01L25/03

CPC classification number: H01L24/05 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3613 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/06181 ,  H01L2224/08113 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1355 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13666 ,  H01L2224/1412 ,  H01L2224/14181 ,  H01L2224/16104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

公开(公告)号：US10276536B2

公开(公告)日：2019-04-30

申请号：US15499962

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

公开(公告)号：US10276402B2

公开(公告)日：2019-04-30

申请号：US15147910

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Feng Chen ,  Chih-Hua Chen ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Hui-Jung Tsai ,  Hao-Yi Tsai

IPC: H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

公开(公告)号：US20190097304A1

公开(公告)日：2019-03-28

申请号：US15717976

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56

Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

公开(公告)号：US10192848B2

公开(公告)日：2019-01-29

申请号：US15712680

申请日：2017-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/525

Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

公开(公告)号：US10115690B2

公开(公告)日：2018-10-30

申请号：US14632654

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Jui Huang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Chien-Ling Hwang

IPC: H01L23/00 ,  C25D1/22 ,  C25D1/00

Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.