公开(公告)号：US20190088660A1

公开(公告)日：2019-03-21

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US20190066746A1

公开(公告)日：2019-02-28

申请号：US15688212

申请日：2017-08-28

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01F10/32 ,  G11C11/15 ,  H01L43/08

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

公开(公告)号：US10210920B1

公开(公告)日：2019-02-19

申请号：US15937317

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xia Li ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: H01L43/08 ,  G11C11/00 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  G11C17/16

Abstract: Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications are disclosed. In exemplary aspects disclosed herein, MTJ devices are fabricated in a semiconductor die to provide at least two different memory arrays. MTJ devices in each memory array are fabricated to have different breakdown voltages. For example, it may be desired to fabricate a One-Time-Programmable (OTP) memory array in the semiconductor die using MTJ devices having a first, lower breakdown voltage, and a separate magneto-resistive random access memory (MRAM) in a same semiconductor die with MTJ devices having a higher breakdown voltage. Thus, in this example, lower breakdown voltage MTJ devices in OTP memory array require less voltage to program, while higher breakdown voltage MTJ devices in MRAM can maintain a desired write operation margin to avoid or reduce write operations causing dielectric breakdown.

公开(公告)号：US10109674B2

公开(公告)日：2018-10-23

申请号：US14822326

申请日：2015-08-10

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L23/528 ,  H01L43/12 ,  G06F17/50 ,  H01L23/522 ,  H01L43/02 ,  H01L43/08

Abstract: A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.

公开(公告)号：US09813049B2

公开(公告)日：2017-11-07

申请号：US14824460

申请日：2015-08-12

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Kan ,  Manu Rastogi ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H03K5/153 ,  H03K3/3565 ,  H03K3/45 ,  H03K3/012 ,  H03K5/24

CPC classification number: H03K3/3565 ,  H03K3/012 ,  H03K3/45 ,  H03K3/455 ,  H03K5/2409 ,  H03K5/2472

Abstract: A particular apparatus includes a magnetic tunnel junction (MTJ) device and a transistor. The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition points that correspond to magnetic switching points of the MTJ device.

公开(公告)号：US09704919B1

公开(公告)日：2017-07-11

申请号：US15192068

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L29/66 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L23/528 ,  H01L23/522 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L27/228 ,  G11C11/16 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L43/12

Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

公开(公告)号：US20170141729A1

公开(公告)日：2017-05-18

申请号：US15417468

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Kan ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H03B15/00

CPC classification number: H03B15/006 ,  G01R33/09 ,  G01R33/1284 ,  G11B5/314 ,  G11B5/3146 ,  G11B5/35 ,  G11B5/3909 ,  G11B2005/0024 ,  G11B2005/3996

Abstract: An apparatus includes a polarizer of a spin-torque oscillator (STO). The polarizer has a perpendicular magnetic anisotropy (PMA) and is configured to receive a first signal having a current density of between 0.51×106 amps per square centimeter (amps/cm2) and 15.3×106 amps/cm2. The apparatus also includes a magnetically soft oscillating region including an antiferromagnetic (AF) coupling layer coupling a first free layer to a second free layer and located between the polarizer and a reference region. The reference region is configured to output a second signal responsive to the first signal, the second signal having a frequency less than 8 gigahertz (GHz).

公开(公告)号：US09646670B2

公开(公告)日：2017-05-09

申请号：US15158658

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Jimmy Kan ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C8/00

CPC classification number: G11C11/1675 ,  G11C8/005 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example, disclosed is a three-terminal magnetic tunnel junction (MTJ) storage element that is programmed via a combination of voltage-controlled magnetic anisotropy (VCMA) and spin-orbit torque (SOT) techniques. Also disclosed is a memory controller configured to program the three-terminal MTJ storage element via VCMA and SOT techniques. The disclosed devices improve efficiency over conventional devices by using less write energy, while having a design that is simpler and more scalable than conventional devices. The disclosed devices also have increased thermal stability without increasing required switching current, as critical switching current between states is essentially the same.

公开(公告)号：US09634237B2

公开(公告)日：2017-04-25

申请号：US14581361

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Jimmy Kan ,  Xiaochun Zhu ,  Matthias Georg Gottwald ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F41/305 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.

公开(公告)号：US09620706B2

公开(公告)日：2017-04-11

申请号：US14558103

申请日：2014-12-02

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Chando Park ,  Jimmy Kan ,  Matthias Georg Gottwald ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L21/02 ,  H01L21/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/12

Abstract: An apparatus includes a capping layer disposed on top of a free layer. The apparatus also includes a magnetic etch stop layer disposed on top of the capping layer. The capping layer and the magnetic etch stop layer are included in a spin-transfer torque magnetoresistive random access memory (STT-MRAM) magnetic tunnel junction (MTJ) device.