公开(公告)号：US10128377B2

公开(公告)日：2018-11-13

申请号：US15441941

申请日：2017-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/535 ,  H01L21/8234

Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.

公开(公告)号：US10121877B1

公开(公告)日：2018-11-06

申请号：US15703130

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method for fabricating a semiconductor device includes forming a semiconductor fin over a substrate. A first doped region is formed on a first end of the semiconductor fin. A second doped region is formed on a second end of the semiconductor fin. An extended contact is formed on the second doped region. A portion of the extended contact extends past an end of the semiconductor fin in a direction orthogonal to a channel of the semiconductor fin. A contact extension is formed on the portion of the extended contact extending past the end of the semiconductor fin. A contact is formed on the first doped region.

公开(公告)号：US09997607B2

公开(公告)日：2018-06-12

申请号：US15198422

申请日：2016-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/42356 ,  H01L21/76251 ,  H01L29/4175 ,  H01L29/66772 ,  H01L29/78654

Abstract: A semiconductor device and method of forming a semiconductor device including an inverted field effect transistor having metal filled front-side source and drain that is self-aligned and in direct contact with a metal filled back-side source and drain, wherein the device includes a metal backgate.

公开(公告)号：US20180006126A1

公开(公告)日：2018-01-04

申请号：US15198422

申请日：2016-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L21/762

CPC classification number: H01L29/42356 ,  H01L21/76251 ,  H01L29/4175 ,  H01L29/66772 ,  H01L29/78654

Abstract: A semiconductor device and method of forming a semiconductor device including an inverted field effect transistor having metal filled front-side source and drain that is self-aligned and in direct contact with a metal filled back-side source and drain, wherein the device includes a metal backgate.

公开(公告)号：US20170221926A1

公开(公告)日：2017-08-03

申请号：US15488613

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US20170170079A1

公开(公告)日：2017-06-15

申请号：US15192021

申请日：2016-06-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Alexander Reznicek ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823807 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: An integrated circuit included n-type FinFETs in an n-region and p-type FinFETs in a p-region. The integrated circuit includes: an n-type fin in the n-region comprising a silicon (Si) fin portion disposed on an oxidized fin portion, the Si fin portion consisting essentially of Si, and the oxidized fin portion consisting essentially of Si, germanium (Ge) and oxygen; and a p-type fin in the p-region consisting essentially of Si and Ge.

公开(公告)号：US20170162443A1

公开(公告)日：2017-06-08

申请号：US14960968

申请日：2015-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49 ,  H01L29/161

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.

公开(公告)号：US09627410B2

公开(公告)日：2017-04-18

申请号：US14718500

申请日：2015-05-21

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L29/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US20170084742A1

公开(公告)日：2017-03-23

申请号：US14856918

申请日：2015-09-17

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76865 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.

公开(公告)号：US20170084713A1

公开(公告)日：2017-03-23

申请号：US14967736

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/7845 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76865 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.