公开(公告)号：US08048588B2

公开(公告)日：2011-11-01

申请号：US10970077

申请日：2004-10-20

Applicant: Sia Kim Tan ,  Soon Yoeng Tan ,  Qunying Lin ,  Huey Ming Chong ,  Liang-Choo Hsia

Inventor： Sia Kim Tan ,  Soon Yoeng Tan ,  Qunying Lin ,  Huey Ming Chong ,  Liang-Choo Hsia

IPC: G03F1/00 ,  G03C5/00 ,  G06F17/50

CPC classification number: G03F1/34 ,  G03F1/36

Abstract: A method and structure for removing side lobes is provided by positioning first and second radiation transparent regions of respective first and second phases at a first plane with the first and second phases being substantially out of phase. Further, positioning the first and the second region to cause radiation at a second plane to be neutralized in a first region, not to be neutralized in a second region, and to have a side lobe in a third region. Further, positioning a non-transparent region at the first plane to assure radiation at the second plane to be neutralized in the first region and positioning a third radiation transparent region of the first or second phase at the first plane to neutralize the side lobes in the third region at the second plane.

Abstract translation: 通过将第一和第二相的第一和第二辐射透明区域定位在第一平面上，其中第一和第二相基本上异相，来提供用于去除旁瓣的方法和结构。 此外，定位第一和第二区域以使第二平面上的辐射在第一区域中被中和，而不在第二区域中被中和，并且在第三区域中具有旁瓣。 此外，在第一平面处定位不透明区域以确保在第二平面处的辐射在第一区域中被中和，并且将第一或第二相的第三辐射透明区域定位在第一平面处以中和旁瓣 第三个地区在第二个飞机。

公开(公告)号：US20110237072A1

公开(公告)日：2011-09-29

申请号：US13158660

申请日：2011-06-13

Applicant: Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

Inventor： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

IPC: H01L21/768

CPC classification number: H01L21/823878 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

Abstract translation: 一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

公开(公告)号：US07960282B2

公开(公告)日：2011-06-14

申请号：US12470028

申请日：2009-05-21

Applicant: Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

Inventor： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

IPC: H01L21/768

CPC classification number: H01L21/823878 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

Abstract translation: 一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

Applicant: Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

Inventor： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC: H01L21/00

CPC classification number: H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

Abstract translation: 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US20100314774A1

公开(公告)日：2010-12-16

申请号：US12860946

申请日：2010-08-23

Applicant: Bei Chao ZHANG ,  Chim Seng SEET ,  Juan Boon TAN ,  Fan ZHANG ,  Yong Chiang EE ,  Bo TAO ,  Tong Qing CHEN ,  Liang Choo HSIA

Inventor： Bei Chao ZHANG ,  Chim Seng SEET ,  Juan Boon TAN ,  Fan ZHANG ,  Yong Chiang EE ,  Bo TAO ,  Tong Qing CHEN ,  Liang Choo HSIA

IPC: H01L23/48

CPC classification number: H01L23/5329 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Abstract translation: 提出了一种形成半导体器件的方法。 该方法包括提供用其上形成的电介质层制备的衬底。 电介质层具有布置在电介质层上部的导线。 处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。

公开(公告)号：US07749894B2

公开(公告)日：2010-07-06

申请号：US11558342

申请日：2006-11-09

Applicant: Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

Inventor： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC: H01L21/4763

CPC classification number: H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract translation: 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US07745320B2

公开(公告)日：2010-06-29

申请号：US12124177

申请日：2008-05-21

Applicant: Jeff Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Hai Cong ,  Hui Peng Koh ,  Mei Sheng Zhou ,  Liang Choo Hsia

Inventor： Jeff Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Hai Cong ,  Hui Peng Koh ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC: H01L29/00 ,  H01L21/311

CPC classification number: H01L29/665 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/78

Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Abstract translation: 描述了在集成电路（IC）中形成硅化物触点的方法。 在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。 这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。 间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

公开(公告)号：US07645687B2

公开(公告)日：2010-01-12

申请号：US11039428

申请日：2005-01-20

Applicant: Yung Fu Chong ,  Dong Kyun Sohn ,  Chew-Hue Ang ,  Purakh Raj Vermo ,  Liang Choo Hsia

Inventor： Yung Fu Chong ,  Dong Kyun Sohn ,  Chew-Hue Ang ,  Purakh Raj Vermo ,  Liang Choo Hsia

IPC: H01L21/322

CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823842

Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.

Abstract translation: 描述了在FUSI设备中制造可变功函数门的实施例。 该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。 选择性外延生长（SEG）用于在源极/漏极区域上形成硅。 掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。 我们提供具有NMOS区和PMOS区的衬底。 我们在所述衬底上形成栅极介电层和栅极层。 我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入到NMOS栅极区域中的栅极层栅极中， 门区域。 我们在所述栅极层上形成覆盖层。 我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。 形成间隔物并形成S / D区域。 在所述衬底表面上沉积金属。 我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

公开(公告)号：US07622403B2

公开(公告)日：2009-11-24

申请号：US11613155

申请日：2006-12-19

Applicant: Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

Inventor： Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

IPC: H01L21/00

CPC classification number: G03F7/0035 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.

Abstract translation: 提供了一种具有超低K电介质的半导体处理系统，包括提供具有电子电路的衬底，在衬底上形成具有致孔剂的超低K电介质层，阻挡来自超低K电介质的第一区域的入射辐射， K电介质层，通过将入射辐射投射在第二区域上，从超低K电介质层的第二区域蒸发致孔剂，并用显影剂除去第一区域中的超低K电介质层。

公开(公告)号：US07615427B2

公开(公告)日：2009-11-10

申请号：US11447565

申请日：2006-06-05

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。