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    Threshold device for a memory array
    91.
    发明授权
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US07995371B2

    公开(公告)日：2011-08-09

    申请号：US11881473

    申请日：2007-07-26

    Applicant: Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    Inventor： Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC: G11C11/00

    CPC classification number: G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    Abstract translation: 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Memory using variable tunnel barrier widths
    93.
    发明授权
    Memory using variable tunnel barrier widths 失效
    使用可变隧道势垒宽度的内存

    公开(公告)号：US07985963B2

    公开(公告)日：2011-07-26

    申请号：US12454698

    申请日：2009-05-21

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    IPC: H01L47/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/02 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/8616 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

    Abstract translation: 公开了一种使用具有可变有效宽度的隧道势垒的存储器。 存储元件包括隧道势垒和导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 形成或破坏低导电性区域。 它可以通过隧道势垒周围的耗尽或过量离子，或通过与互补离子组合的移动离子来形成。 可能通过反转成形过程或减少隧道势垒并将离子注入导电材料来破坏。 低导电率区域增加了隧道势垒的有效宽度，使得电子隧道更大的距离，这降低了存储元件的导电性。 通过改变电导率，可以在存储器单元中产生多个状态。

    Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory
    94.
    发明申请
    Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory 审中-公开
    集成电路包括四层垂直堆叠嵌入式可重写非易失性双端存储器

    公开(公告)号：US20110080767A1

    公开(公告)日：2011-04-07

    申请号：US12928239

    申请日：2010-12-06

    Applicant: Darrell Rinerson ,  Christoophe J. Chevallier ,  Steve Kuo-Ren Hsia

    Inventor： Darrell Rinerson ,  Christoophe J. Chevallier ,  Steve Kuo-Ren Hsia

    IPC: G11C11/00

    CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

    Abstract translation: 公开了一种整体形成在包括有源电路的基板的顶部上的多层非易失性存储器。 每层存储器包括具有多电阻状态材料层的存储器单元（例如，两端存储单元），其在存储单元上施加写入电压时在低电阻状态和高电阻状态之间改变其电阻状态 。 可以通过在存储器单元上施加读取电压来非存储性地确定存储单元中存储的数据。 数据存储容量可以通过增加或减少在衬底上整体制造的存储层的数量（例如，四层以上或者四层以下）来适应特定应用。 存储器单元可以包括仅在读取和写入操作期间允许访问存储器单元的非欧姆器件。 每个存储器层可以包括交叉点阵列。

    Device fabrication
    95.
    发明申请
    Device fabrication 失效
    器件制造

    公开(公告)号：US20100159688A1

    公开(公告)日：2010-06-24

    申请号：US12454322

    申请日：2009-05-15

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    Movable terminal in a two terminal memory array
    96.
    发明授权
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US07701834B2

    公开(公告)日：2010-04-20

    申请号：US11037971

    申请日：2005-01-18

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    IPC: G11B9/00

    CPC classification number: G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    Abstract: A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    Abstract translation: 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

    Method for two-cycle sensing in a two-terminal memory array having leakage current
    98.
    发明授权
    Method for two-cycle sensing in a two-terminal memory array having leakage current 有权
    具有漏电流的双端存储器阵列中的双周期感测方法

    公开(公告)号：US07436723B2

    公开(公告)日：2008-10-14

    申请号：US12074448

    申请日：2008-03-03

    Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C7/02

    CPC classification number: G11C11/16 ,  G11C13/004 ,  G11C2013/0057

    Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

    Abstract translation: 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

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