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    Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes
    2.
    发明授权
    Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes 有权

    公开(公告)号：US11664824B2

    公开(公告)日：2023-05-30

    申请号：US16476599

    申请日：2018-01-09

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Amirpasha Shirazinia ,  Mattias Andersson ,  Magnus Malmberg ,  Sara Sandberg

    IPC分类号： H03M13/11 ,  H03M13/00 ,  H03M13/33

    CPC分类号： H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/616

    摘要： According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques. This may be achieved by keeping the memory access and processing hardware units active simultaneously to avoid excess decoding latency. More specifically, certain embodiments may carry out memory access and computation process simultaneously, without any effort to make the row layers mutually orthogonal to each other. Another technical advantage may be that the proposed decoding algorithm adjusts the LLRs to partially account for deviations from the layered decoding due to non-orthogonal rows.

    ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE
    3.
    发明申请
    ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE 有权

    公开(公告)号：US20210359707A1

    公开(公告)日：2021-11-18

    申请号：US17381973

    申请日：2021-07-21

    申请人： FUJITSU LIMITED

    发明人： KAZUMASA MIKAMI ,  Junichi Sugiyama

    IPC分类号： H03M13/25 ,  H03M13/11 ,  H03M13/31 ,  H03M13/33

    摘要： An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

    ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE
    4.
    发明申请
    ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE 有权

    公开(公告)号：US20210075444A1

    公开(公告)日：2021-03-11

    申请号：US16996967

    申请日：2020-08-19

    申请人： FUJITSU LIMITED

    发明人： KAZUMASA MIKAMI ,  Junichi Sugiyama

    IPC分类号： H03M13/11 ,  H03M13/25 ,  H03M13/33 ,  H03M13/31

    摘要： An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

    ENCODER SIGNAL PROCESSING DEVICE, ENCODER, AND SIGNAL PROCESSING METHOD AND RECORDING MEDIUM
    8.
    发明申请
    ENCODER SIGNAL PROCESSING DEVICE, ENCODER, AND SIGNAL PROCESSING METHOD AND RECORDING MEDIUM 审中-公开

    公开(公告)号：US20180041231A1

    公开(公告)日：2018-02-08

    申请号：US15666975

    申请日：2017-08-02

    申请人： FANUC CORPORATION

    发明人： Youhei KONDOU

    IPC分类号： H03M13/33 ,  H03M13/00

    CPC分类号： H03M13/33 ,  G01D5/00 ,  G01D5/2449 ,  G01D5/24495 ,  H03M13/615

    摘要： An encoder signal processing device detects position data at every predetermined time interval from an original signal which is an analog amount generated in an encoder according to movement of a measurement target. The encoder signal processing device includes: an approximate curve calculation unit that calculates an approximate curve of a detection error included in the original signal on the basis of the detection error of the position data at at least three or more points; an approximate error computation unit that computes an approximate value of the detection error of the position data at an arbitrary time point on the basis of the approximate curve of the detection error; and a position data correction unit that corrects the detection error of the position data at the arbitrary time point on the basis of the approximate value of the detection error of the position data.