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    PATH ENCODING AND DECODING
    3.
    发明申请
    PATH ENCODING AND DECODING 有权

    公开(公告)号：US20170170843A1

    公开(公告)日：2017-06-15

    申请号：US15437500

    申请日：2017-02-21

    Applicant: International Business Machines Corporation

    Inventor： Frederic J. Bauchot ,  Marc Joel Herve Legroux

    IPC: H03M7/30

    CPC classification number: H03M7/3084 ,  G06F12/0207 ,  H03M5/00 ,  H03M5/14 ,  H03M7/00 ,  H03M7/30 ,  H03M7/40 ,  H03M7/4025 ,  H03M9/00 ,  Y02D10/13

    Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

    PATH ENCODING AND DECODING
    5.
    发明申请
    PATH ENCODING AND DECODING 有权

    公开(公告)号：US20160182085A1

    公开(公告)日：2016-06-23

    申请号：US14947101

    申请日：2015-11-20

    Applicant: International Business Machines Corporation

    Inventor： Frederic J. Bauchot ,  Marc Joel Herve Legroux

    IPC: H03M9/00 ,  G06F17/22 ,  H03M7/14

    CPC classification number: H03M9/00 ,  G06F17/2217 ,  H03M5/00 ,  H03M7/14 ,  H03M7/30 ,  H03M7/40 ,  H03M7/4025

    Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE
    6.
    发明申请
    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE 有权
    数字编码并行总线同时抑制同时开关输出噪声

    公开(公告)号：US20160164539A1

    公开(公告)日：2016-06-09

    申请号：US14563485

    申请日：2014-12-08

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

    IPC: H03M13/21 ,  G06F11/16

    CPC classification number: G06F11/1625 ,  G06F11/00 ,  H03M5/00 ,  H03M7/00 ,  H03M13/09

    Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许发送数据的不同编码级别。 该装置可以包括编码器单元和多个收发器单元。 编码器单元可以被配置为接收多个数据字，其中每个数据字包括N个数据位，其中N是大于1的正整数，并且对多个数据字的第一数据字进行编码。 编码的第一数据字可以包括M个数据位，其中M是大于N的正整数。每个收发器单元可以发送编码的第一数据字的相应数据位。 编码器单元还可以被配置为接收指示编码的第一数据字的传输质量的信息，并且根据质量来编码多个数据字中的第二数据字。

    INSTRUCTION AND LOGIC FOR HARDWARE COMPRESSION WITH TILED DATA STRUCTURES OF DISSIMILAR DIMENSIONS
    7.
    发明申请
    INSTRUCTION AND LOGIC FOR HARDWARE COMPRESSION WITH TILED DATA STRUCTURES OF DISSIMILAR DIMENSIONS 审中-公开
    硬件数据结构的硬件压缩指令和逻辑

    公开(公告)号：US20160092112A1

    公开(公告)日：2016-03-31

    申请号：US14496300

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： Hasmet Akgun ,  Premkishore Shivakumar ,  Deepak Limaye

    IPC: G06F3/06

    CPC classification number: G06F9/44 ,  G06F3/06 ,  H03M5/00 ,  H03M7/30 ,  H03M7/3079

    Abstract: An apparatus includes a controller and a compression unit. The controller includes logic to receive an input line of data from a data producer and divide the input line of data into a plurality of segment. Each segment corresponds to a compression context and to a multi-line data tile. The controller also includes logic to write a first segment of the input line to a first multi-line data tile, and to write a second segment of the input line to a second multi-line data tile upon reaching a boundary of the first multi-line data tile. The compression unit includes logic to apply a first compression context to the first multi-line data tile and a second compression context to the second multi-line data tile.

    Abstract translation: 一种装置包括控制器和压缩单元。 控制器包括从数据生成器接收数据的输入行并将输入数据线划分成多个段的逻辑。 每个段对应于压缩上下文和多行数据块。 控制器还包括将输入线的第一段写入第一多行数据块的逻辑，并且在到达第一多行数据块的边界时将输入线的第二段写入第二多行数据块， 线数据瓦片。 压缩单元包括将第一压缩上下文应用于第一多行数据块的逻辑，以及将第二压缩上下文应用于第二多行数据块。

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