INSTRUCTION AND LOGIC FOR HARDWARE COMPRESSION WITH TILED DATA STRUCTURES OF DISSIMILAR DIMENSIONS
    1.
    发明申请
    INSTRUCTION AND LOGIC FOR HARDWARE COMPRESSION WITH TILED DATA STRUCTURES OF DISSIMILAR DIMENSIONS 审中-公开
    硬件数据结构的硬件压缩指令和逻辑

    公开(公告)号:US20160092112A1

    公开(公告)日:2016-03-31

    申请号:US14496300

    申请日:2014-09-25

    CPC classification number: G06F9/44 G06F3/06 H03M5/00 H03M7/30 H03M7/3079

    Abstract: An apparatus includes a controller and a compression unit. The controller includes logic to receive an input line of data from a data producer and divide the input line of data into a plurality of segment. Each segment corresponds to a compression context and to a multi-line data tile. The controller also includes logic to write a first segment of the input line to a first multi-line data tile, and to write a second segment of the input line to a second multi-line data tile upon reaching a boundary of the first multi-line data tile. The compression unit includes logic to apply a first compression context to the first multi-line data tile and a second compression context to the second multi-line data tile.

    Abstract translation: 一种装置包括控制器和压缩单元。 控制器包括从数据生成器接收数据的输入行并将输入数据线划分成多个段的逻辑。 每个段对应于压缩上下文和多行数据块。 控制器还包括将输入线的第一段写入第一多行数据块的逻辑,并且在到达第一多行数据块的边界时将输入线的第二段写入第二多行数据块, 线数据瓦片。 压缩单元包括将第一压缩上下文应用于第一多行数据块的逻辑,以及将第二压缩上下文应用于第二多行数据块。

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