摘要:
This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
摘要:
The invention relates to a method of encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal. The stream of data bits of the source signal is divided into a sequence of five permissible source words of variable length. Each of these five permissible source words is converted into a channel word with twice the number of data bits. This conversion has been selected in such a way that the error propagation is very small and the electronics can be very simple.
摘要:
An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 1 bit of unconstrained into 2 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of three future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 3 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
摘要:
Framing or block synchronization of digital information signals grouped in blocks of variable length is provided by preceding each block with a synchronization code word. Each synchronization code word is error correction encoded in accordance with a BCH code to indicate the number of information bits in the following block and, hence, the location of the next succeeding synchronization code word. Since only the synchronization code words are error correction encoded, they can be distinguished from the information bits to obtain synchronization. A synchronization receiver acquires synchronization upon the occurrence of an error-free synchronization code word in the incoming signal. Synchronization is maintained thereafter by utilizing the inherent error correction capability offered by the BCH code to correct up to two errors in each received synchronization code word before decoding it to locate the next synchronization word. If, however, three errors are detected in a received synchronization word, synchronization is assumed to be lost and synchronization is thereafter recovered with the occurrence of a succeeding error-free synchronization code word in the incoming digital signal. Two receiver embodiments are disclosed which perform the above-described operation. The first embodiment is adapted to perform a general type of framing synchronization, while the other embodiment is specifically adapted to provide video synchronization.
摘要:
In the transmission of variable length frames of digital information separated by one or more flag sequences, a block check is generated and appended to the information bits at the transmitter. The block check is generated by Exclusive OR''ing a predetermined non-zero number to the high order information bits and generating (n-k) check digits according to a cyclic error detecting code. The (n-k) check digits are Exclusive OR''d with an (n-k) bit non-zero number to produce the block check. At the receiver, the first mentioned non-zero number is added to the high order information bits and an (n-k) digit number is generated according to the same cyclic error detecting code used at the transmitter. This number is checked to see if it conforms to a predetermined number indicating error-free transmission. Utilizing the above approach, transmission errors in or near the flag sequence are detected, as well as those which may occur in the information field.
摘要:
This data processing technique utilizes compacted data in the form of variable-length codes having length-representing prefix portions which themselves are variable-length encoded. The relatively small amount of storage needed when such a code format is used enables data to be conveniently encoded and handled as groups of characters rather than as single characters. The variable-length prefixes are decoded by a small, fast, searchonly type of associative memory which furnishes a matchindicating signal as an address to another memory having conventional storage elements. The output of the latter may contain a base address in still another memory of conventional type and an indication of how many bits remain in the current variable-length code word. These remaining bits furnish a displacement value which, in combination with the base address, will locate the decoded fixed-length word or character group in the last memory unit. In those instances where the length of the variable-length codes would become excessively long (for the less frequently occurring character groups) the original fixed-length codes are employed, each being preceded by a common ''''COPY'''' code. A special decoding procedure is invoked by this copy code.